Intel Corporation

Ed Grochowski

Hong Wang

John Thomas Shen

Gautham N Chinya

Richard A Hankins

James Paul Held

Baiju V Patel

Per H Hammarlund

Scott Dion Rodgers

Prashant Sethi

Shivnandan D Kaushik

Bryant E Bigbee

Xiang Chris Zou

Perry H Wang

Xinmin Tian

Anil Aggarwal

Sanjiv M Shah

Ryan N Rakvic

David K Poulsen

Murali M Annavaram

Wei Ey Li

Derrick Chu Lin

John P Shen

Partha Kundu

Jamison D Collins

Tin-Fook Ngai

Roger Gramunt

Roger Espasa

Gerolf F Hoflehner

Rolf Kassa

Julio Gago

Raya Leviathan

Nimish H Modi

Marsha Eng

Alejandro Ramirez

Charkravaythy Kosaraju

Champa R Yellamilli

Dan Lavery

A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Method and system to provide user-level multithreading

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

Method, system, and apparatus for page sizing extension

A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Load balancing for multi-threaded applications via asymmetric power throttling

In one embodiment, the invention provides a method for examining information about branch instructions. A method, comprising: examining information about branch instructions that reach a write-back stage of processing within a processor, defining a plurality of streams based on the examining, wherein each stream comprises a sequence of basic blocks in which only a last block in the sequence ends in a branch instruction, the execution of which causes program flow to branch, the remaining basic blocks in the stream each ending in a branch instruction, the execution of which does not cause program flow to branch.

Apparatus to implement mesocode

A microprocessor that handles invalid opcodes via an event-signaling micro-operation is disclosed. The microprocessor comprises a decoder that decodes macroinstructions, including an opcode, into a single microprocessor cycle micro-operation. The decoder detects invalid opcodes and replaces the invalid opcodes with an event-signaling micro-operation that triggers an invalid opcode assist. The invalid opcode assist triggers an invalid opcode exception handler that processes the invalid opcode.

Method and apparatus for handling invalid opcode faults via execution of

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San Jose, CA, United States of America

Ed Grochowski