Infineon Technologies Ag

Intel Corporation

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Eckhard Delfs

Gerard David Jennings

Hong Wang

Per H Hammarlund

Gautham N Chinya

Perry H Wang

Stephen J Robinson

Deepak A Mathaikutty

Uma Satya Ranjan

Thiam Wah Loh

Andreas Wasserbauer

Reza Fortas

Andreas Siggelkow

Swee Chong Peter Kuan

Chee Weng Tan

Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

Hardware-assisted virtualization for implementing secure video output path

Computing device with a processing system including a plurality of user sub-systems, a plurality of user sub-system identifiers respectively identifying one user sub-system of the plurality of user sub-systems, a processor configured to run the processing system, a cryptography unit configured to provide at least one cryptographic mechanism, a cryptography unit secret key assigned to the cryptography unit, and a binder configured to bind the cryptography unit secret key to the user sub-system identifier of a currently running user sub-system.

Computing device, with data protection

A data processing system including a memory configured to store confidential data and non-confidential data; a cache memory which is configured to cache data stored in the memory and which comprises a first cache memory region and a second cache memory region; a processing circuit configured to carry out, in a first state of the data processing system, a cryptographic algorithm which operates on the confidential data and on the non-confidential data, wherein the confidential data are cached using the first cache memory region and the non-confidential data are cached using the second cache memory region; and an invalidating circuit configured to invalidate the first cache memory region when the data processing system switches from the first state into a second state.

Data processing system, method for executing a cryptographic algorithm and method for preparing execution of a cryptographic algorithm

Processor arrangement having a first processor, a second processor, and at least one memory configured to be shared by the first processor and the second processor. The second processor has a memory interface configured to provide access to the at least one memory, and a processor communication interface configured to provide a memory access service to the first processor. The first processor has a processor communication interface configured to use the memory access service from the second processor. The first processor and the second processor use at least one cryptographic mechanism in the context of the memory access service.

Secure processor arrangement having shared memory

A first time indication which can be changed by a user and stored in a first memory. Furthermore, in the case of a change in the first time indication which is performed externally to the checking device, the difference between the stored first time indication and the changed first time indication is determined. Furthermore, it is checked whether a predetermined criterion is met by using a trustworthy second time indication, the first time indication and the difference.

Time data checking unit, electronic device and method for checking a time indication

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Nuremberg, Germany

Eckhard Delfs