Infineon Technologies Ag

Eckehard Pl&auml;ttner

Aaron Nygren

Andreas T&auml;uber

Manfred Plan

Robert Fuerle

A semiconductor memory apparatus includes a memory cell array having a multiplicity of data lines and a multiplicity of local amplifiers, each of the local amplifiers being associated with a data line. An amplifier group includes at least two amplifiers selected from the multiplicity of local amplifiers. Each amplifier has at least a pair of selection transistors for selecting a particular amplifier from the amplifier group. The selection transistors have a common gate, an unshared intrinsic diffusion region, and a shared intrinsic diffusion region, the shared intrinsic diffusion region being shared with an adjacent selection transistor from an adjacent amplifier.

Semiconductor memory apparatus

The electrical circuit includes a plurality of circuit components which are connected via a bus. At least one of the circuit components can be tested independently of the other circuit components. The circuit component which is to be tested and the method for testing the circuit component are distinguished in that steps are taken to ensure that, during testing, the circuit component which is tested, outputs no data to the bus, and/or instead of the data which would need to be output to the bus during normal operation, outputs other data to the bus.

Growing community of inventors

Oberhaching, Germany

Eckehard Plättner

Growing community of inventors

Oberhaching, Germany

Eckehard Pl&auml;ttner

Eckehard Plättner