Texas Instruments Corporation

Echere Iroaga

Ashish Manjrekar

Bryan E Bloodworth

Indumini W Ranmuthu

Paul Merle Emerson

Patrick Michael Teterud

Charles H Sobey

Glenn C Mayfield

Ashish Manjreka

An apparatus for providing a read signal at an output locus for access by an information processing device receives an input signal containing the information; the apparatus includes: (a) a read signal control unit receiving the input signal at a control unit input locus; the control unit is coupled with the output locus and controls the read signal; (b) a plurality of switches; and (c) a plurality of bias arrays coupled with the switches. A first bias array set cooperates with the plurality of switches in a first orientation to couple the first bias array set with the control unit to establish a first operational mode. A second bias array set cooperates with the plurality of switches in a second orientation to couple the second bias array set with the control unit to establish a second operational mode.

Apparatus and method for providing a read signal for an information processing device

An improved bias circuit for a disk drive head which reduces or eliminates transients while switching biasing. Embodiments of the invention are directed to eliminating transients while switching the bias of a MR head such as from current bias to voltage biasing. In an embodiment of the present invention, bias enable signals from a control circuit are inputs to delay circuits. The delay circuits provide a delay on the high-to-low transition, and essentially no delay on the low-to-high transition. The unsymmetrical delay ensures that the read head bias current will continue to be driven during the biasing transition to reduce voltage swings that could damage the head.

Method and circuit for eliminating glitches in a disk drive read head

The present invention relates to a method of enhancing a preamplifier read recovery in a hard disk drive system and comprises the steps of determining whether the hard disk drive system is transitioning from a non-read state to a read state and initiating a non-read state to a read state transition sequence when a transition from the non-read state to the read state is determined. The transition sequence is independent of a type of non-read state prior to the transitioning. After the non-read state to read state transition sequence is complete the read mode is initiated. In addition, the invention comprises a system for controlling a transition from a non-read state to a read state associated with a preamplifier in a hard disk drive system. The system comprises a detection circuit operable to detect a completion of the non-read state and a non-read state to read state circuit operable to execute a series of events to transition from the non-read state to the read state, wherein the series of events is the same regardless of a type of non-read state. Further, the system comprises a read state initiation circuit operable to initiate the read state after the execution of the series of events.

Preamplifier read recovery parade

A method and circuit for selectively timing amplifier stages of a multi-stage reader amplifier for a hard disk drive system. The reader amplifier includes a first stage, second stage and third stage coupled in series. The method includes the steps of powering the first stage, delaying the enabling of the second stage, and delaying the enabling of the third stage, in order to reduce excursions on the third stage output signal. The circuit includes a logic circuit for successively enabling the second and third amplifier stages.

Relative timing sequence for reader amplifiers

An adjustable impedance boosting circuit for a magneto-resistive head in a gain stage beyond the input gain stage. The boosting circuit compensates for a frequency pole of the head leads by introducing a zero in proportion to the resistance of the magneto-resistive element and with selectable circuit parameters to further adjust the pole compensation. The invention includes selectively adjusting the sensitivity of the pole compensation to changes in the resistance of the head, selectively adjusting the peak compensation, and adjusting the frequency of the compensating zero.

Input pole compensation for a disk drive read head

A differential circuit to read differential data from a disk by a voltage bias includes a read circuit to read the differential data from the disk by maintaining the voltage bias by a first transistor and a second transistor, the first transistor being positioned in a first current path to maintain a first current and the second transistor being positioned in a second current path to maintain a second current. The first current is approximately equal to the second current.

Preamp reader design for high resistance read heads

A circuit ( ) and method ( ) for protecting read heads ( ) of a hard-disk drive system ( ). Capacitor C is controllably coupled to a dummy head R during a V mode, so that capacitor C has a low, predictable voltage upon returning to I mode, protecting the read heads ( ) from damage. The circuit ( ) includes logic ( ) and algorithm ( ) determining when to couple the capacitor C to the dummy head R during a servo bank write (SBW) sequence.

Read head protection circuit and method

A preamplifier circuit for a hard disk drive system comprises a preamplifier circuit having a bias voltage circuit stage associated therewith. The preamplifier circuit further comprises a current bias boost recovery circuit operatively coupled to the bias voltage circuit stage which is configured to increase a rate of charging of a noise reduction capacitor associated with the bias voltage circuit stage. A head select boost recovery circuit is also operatively coupled to the bias voltage circuit and is configured to increase a rate of charging or discharging of a bias capacitor associated with the bias voltage circuit stage. Together the circuits allow for a concurrent head switch and current bias switch and avoids the problems associated with the prior art.

Capacitor bias recovery methodology

A selectively adjustable impedance boosting circuit for a magneto-resistive head in a disk drive to compensate a frequency pole by introducing a zero in proportion to the resistance of the magneto-resistive element and with selectable circuit parameters to further adjust the pole compensation. The invention includes selectively adjusting the sensitivity of the pole compensation to changes in the resistance of the head, selectively adjusting the peak compensation, and adjusting the frequency of the compensating zero.

Selectable input pole compensation for a disk drive read head

An offset circuit to correct an offset between differential signals includes a read circuit to read the differential signals, a circuit to measure the offset of the differential signals, and a programmable trim circuit to compensate for the offset of said differential signals.

Write to read switching time trim circuit

An integrated circuit having a pinout configuration, having a first configuration of pins and a circuit to change the integrated circuit to a second configuration of pins.

Fuse selectable pinout package

A magneto-resistive head preamplifier structure has a difference amplifier with cross-coupled transistors configured to cancel the adverse effects on preamplified output signals due to parasitic capacitance associated with the difference amplifier transistors. The cross-coupled transistors extend the useable bandwidth of the preamplifier by substantially reducing internally generated thermal noise.

Low noise magneto-resistive read head preamplifier

A hard disk drive system (10) includes a read head (21) for reading information from a rotating magnetic disk (12). The read head outputs a servo burst signal in response to servo information (59) on the disk. An analog-to-digital converter (33) is provided to oversample the servo burst signal during each of a plurality of successive time intervals, in order to obtain a plurality of samples for each such time interval. An accumulator (74) is provided to sum the samples for each time interval, in order to obtain for each time interval a respective accumulation value that represents an integration of the burst signal for that time interval. A filtering circuit (86) is provided to determine a burst value for the servo burst signal, by applying a filtering function to a set of the accumulation values. The filtering function may involve determining a median accumulation value from the set of accumulation values, or determining a mean of the accumulation values in the set.

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Garland, TX, United States of America

Echere Iroaga