University of Rochester

Technion Research & Development Foundation Ltd

Synopsys, Inc.

University of South Florida

Tasit, LLC

Eby G Friedman

Engin Ipek

Mohammad Kazemi

Ravi Patel

Radu Mircea Secareanu

Volkan Kursun

Xiaochen Guo

Kamil Pas

Ji Liu

Isaac Richter

Avinoam Kolodny

Mikhail Popovich

Abdelrahman G Qoutb

Jamil Kawa

Olin L Hartin

Ran Ginosar

Shahar Kvatinsky

Selcuk Kose

Stephen Robert Whiteley

Arkadiy Morgenshtein

Ben Feinberg

Mahdi Nazm Bojnordi

Robert E Freeman

Inna Vaisband

Guoqing Chen

Shibo Wang

Jonathan Rosenfeld

Albert Ciprut

Mucahit Kozak

Yehea Ismail

On-chip testing of a superconductive integrated circuit device includes receiving a superconductive circuit design having superconductive logic elements. Further, a first testability characteristic for first test circuitry at a first node within the superconductive circuit design is determined. The first testability characteristic corresponds to one or more of a test generation control level and a test observability control level. An updated superconductive circuit design from the superconductive circuit design is generated based on the first testability characteristic for the first test circuitry. The superconductive circuit design includes the first test circuitry at the first node.

Superconductive integrated circuit devices with on-chip testing

A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current Jthrough a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current Joff after tseconds, where an effective field experienced by the magnetization of the ferromagnetic layer His significantly dominated by and in-plane anisotropy H, and where M passes a hard axis by precessing around the H; and passing the hard axis, where His dominated by a perpendicular-to-the-plane anisotropy H, and where M is pulled towards the new equilibrium state by precessing and damping around H, completing a magnetization switching.

Switching of perpendicularly magnetized nanomagnets with spin-orbit torques in the absence of external magnetic fields

A base element for switching a magnetization state of a nanomagnet includes a heavy-metal nanostrip having a surface. The heavy-metal nanostrip includes at least a first layer including a heavy metal and a second layer which includes a different heavy-metal. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet includes a shape having a long axis and a short axis, the ferromagnetic nanomagnet having both a perpendicular-to-the-plane anisotropy Hand an in-plane anisotropy Hand the ferromagnetic nanomagnet having a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable by a flow of electrical charge through the heavy-metal nanostrip. A direction of the flow of electrical charge through the heavy-metal nanostrip includes an angle &#x3be; with respect to the short axis of the nanomagnet.

A hybrid integrated thermal sensor device includes a magnetic tunnel junction (MTJ) device electrically coupled in series with at least one CMOS transistor and disposed between a voltage rail terminal and a ground terminal. An output terminal is electrically coupled to a drain of the at least one CMOS transistor. The MTJ operates in an anti-parallel state and the output terminal provides a voltage indicative of a temperature of the MTJ device based on an MTJ antiparallel resistance. A distributed sensor network for real-time thermal mapping of an integrated circuit (IC) is also described.

Distributed spintronic/CMOS sensor network for thermal aware systems

A method to adaptively and dynamically set a bias scheme of a crossbar array for a write operation includes: performing a read-before-write operation to determine a number of cells n to be written during a write operation; comparing n to a predetermined threshold value to determine an efficient bias scheme; setting at least one voltage regulator to provide a bias voltage according to the efficient bias scheme; and performing the write operation. A method to determine threshold value to determine an efficient bias scheme of a crossbar array and an energy efficient crossbar array device are also described.

Energy efficient write scheme for non-volatile resistive crossbar arrays with selectors

A base element for switching a magnetization state of a nanomagnet includes a heavy-metal nanostrip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet includes a shape having a long axis and a short axis. The ferromagnetic nanomagnet has both a perpendicular-to-the-plane anisotropy Hand an in-plane anisotropy Hand the ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable by a flow of electrical charge through the heavy-metal nanostrip. A direction of flow of the electrical charge through the heavy-metal nanostrip includes an angle &#x3be; with respect to the short axis of the nanomagnet.

An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.

Superconducting system architecture for high-performance energy-efficient cryogenic computing

A base element for switching a magnetization state of a nanomagnet includes a heavy-metal strip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable in an absence of an external magnetic field by a flow of electrical charge through the heavy-metal strip. A method for switching a magnetization state of a nanomagnet is also described.

Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Resistive memory accelerator

A method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

A heterogeneous power distribution system for an integrated circuit includes a power network-on-chip that receives electrical power from one or more off-chip power converters. The power network-on-chip includes a mesh of power routers to power a plurality of on-chip loads. The mesh of power routers includes a plurality of integrated simple routers and a plurality of integrated complex power routers. Each complex power router of the plurality of complex power routers includes a microcontroller which is communicatively coupled to one or more switches and one or more sensors of the complex power router. The microcontroller is configured to run a process algorithm that dynamically routes and controls power according to a power delivery policy by controlling the one or more switches based on information received from the one or more sensors. A method to determine a near optimal distribution of power supply resources in a heterogeneous power delivery system is also described.

Heterogeneous method for energy efficient distribution of on-chip power supplies and power network on-chip system for scalable power delivery

A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.

Multistate register having a flip flop and multiple memristive devices

The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.

Digitally controlled wide range pulse width modulator

A method for modifying a logic circuit layout to optimize circuit propagation delays for improved circuit operation is presented. The layout includes multiple logic gates connected by conductive segments. An initial layout of a physical electronic logic circuit having the plurality of logic gates is input. A respective size is determined for each of the logic gates in accordance with the initial layout and a circuit propagation delay criterion. The circuit propagation delay criterion is a joint function of properties of at least some of the logic gates and at least some of the conductive segments. A modified logic circuit layout is output. The modified logic circuit layout includes a layout of the logic gates arranged in accordance with the initial layout, where each of the logic gates is modified according to the respective determined size, thereby to obtain a modification of the logic circuit layout incorporating an optimized circuit propagation delay.

Growing community of inventors

Rochester, NY, United States of America

Eby G Friedman