Intel Corporation

Qorvo Us, Inc.

Other

Axcelis Technologies, Inc.

Ebrahim Andideh

Daniel C Diana

Chia-Hong Jan

Robert S Chau

Mark T Bohr

Michael J Leeson

Hitesh Windlass

Kevin L Peterson

Peter K Moon

Makarem A Hussein

Lawrence D Wong

Julie A Tsai

Scott E Thompson

Lawrence N Brigham

Mark R Richards

Mitch C Taylor

Qing Ma

Valery M Dubin

Alan M Myers

Quan Anh Tran

Richard E Green

Steven N Towle

Daniel N Sobieski

Matthew J Prince

Mohsen Alavi

Lee D Rockford

Mark Isenberger

Vinodhkumar Raghunathan

Wayne K Ford

Steve Towle

Clark Cummins

Larry Wong

Tahir Ghani

Anand S Murthy

Patrick R Morrow

Robert Aigner

Richard L Coulson

Digvijay Ashokkumar Raorane

Weng Hong Teh

R Scott List

Dilan Seneviratne

Buu Quoc Diep

Carlo Waldfried

Robert Kraft

Jeffery D Bielefeld

Mitchell C Taylor

Sam Sivakumar

Qingyuan Han

Ian Y Yee

Orlando Escorcia

Matthew Wasilik

Arnel M Fajardo

Seiichi Morimoto

Donald D Danielson

Ming Fang

Justin S Sandford

Emile Davies-Venn

Kevin R Weldon

Robert J Patterson

Deepak Arora

Bang Nguyen

Changmin Park

Mani Rahnama

Jeff Bielefeld

James C Meyer

Wilmer F Borger

Jeffrey T West

Richard M Steger

William C Hicks

Sarah Bowen

The present disclosure relates to a Wafer-Level-Packaged (WLP) Bulk Acoustic Wave (BAW) device that includes a BAW resonator, a WLP enclosure, and a surface mount connection structure. The BAW resonator includes a piezoelectric layer with an opening and a bottom electrode lead underneath the piezoelectric layer, such that a portion of the bottom electrode lead is exposed through the opening of the piezoelectric layer. The WLP enclosure includes a cap and an outer wall that extends from the cap toward the piezoelectric layer to form a cavity. The opening of the piezoelectric layer is outside the cavity. The surface mount connection structure covers a portion of a top surface of the cap and extends continuously over a side portion of the WLP enclosure and to the exposed portion of the bottom electrode lead through the opening of the piezoelectric layer.

Wafer-level-packaged BAW devices with surface mount connection structures

Stealth-dicing-compatible devices and methods to prevent acoustic backside reflections on acoustic wave devices are disclosed. An acoustic wave device comprises a substrate having opposing top and bottom surfaces, where a first portion of the bottom surface has a higher roughness than a second portion of the bottom surface, and an acoustic resonator over the top surface of the substrate. The acoustic resonator comprises a piezoelectric layer having opposing top and bottom surfaces and a plurality of electrodes, at least some of which are disposed on the top surface of the piezoelectric layer. The first portion of the bottom surface of the substrate is below and opposite from the acoustic resonator, and the second portion of the bottom surface of the substrate is not located below and opposite from the acoustic resonator. Multiple first portions, each separated from the other by second portions, may exist.

Stealth-dicing compatible devices and methods to prevent acoustic backside reflections on acoustic wave devices

Embodiments of the present disclosure are directed towards techniques and configurations for formation of a dielectric with a smooth surface. In one embodiment, a method includes providing a dielectric with first and second surfaces, a conductive feature formed on the first surface, and a laminate applied to the second surface, curing the second surface while the laminate remains applied, and removing the laminate. Other embodiments may be described and/or claimed.

Formation of dielectric with smooth surface

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

Methods of providing dielectric to conductor adhesion in package structures

Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.

Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer

Ferroelectric polymer memory modules are described. In an example, a module has a first set of layers including a first ILD layer defining trenches therein, a first electrode layer disposed in the trenches of the first ILD layer, a first conductive polymer layer disposed on the first electrode layer and in the trenches of the first ILD layer, and a ferroelectric polymer layer disposed on the first conductive polymer layer, in and extending beyond the trenches of the first ILD layer. The module also has a second set of layers disposed on the first set of layers to define memory cells therewith. The second set of layers includes a second ILD layer defining trenches therein, a second conductive polymer layer disposed in the trenches of the second ILD layer, and a second electrode layer disposed on the second conductive polymer layer.

Ferroelectric polymer memory module

A ferroelectric polymer memory module includes a first set of layers including: a first ILD layer defining trenches therein; a first electrode layer disposed in the trenches of the first ILD layer; a first conductive polymer layer disposed on the first electrode layer and in the trenches of the first ILD layer; and a ferroelectric polymer layer disposed on the first conductive polymer layer and in the trenches of the first ILD layer; and a second set of layers disposed on the first set of layers to define memory cells therewith, the second set of layers including: a second ILD layer defining trenches therein; a second conductive polymer layer disposed in the trenches of the second ILD layer; and a second electrode layer disposed on the second conductive polymer layer.

According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.

Method of reducing the surface roughness of spin coated polymer films

A technique includes forming overlaying magnetic metal layers over a semiconductor substrate. The technique includes forming at least one resistance layer between the magnetic metal layers.

Laminating magnetic materials in a semiconductor device

In accordance with some embodiments, a ferroelectric polymer memory may be formed of a plurality of stacked layers. Each layer may be separated from the ensuing layer by a polyimide layer. The polyimide layer may provide reduced layer-to-layer coupling, and may improve planarization after the lower layer fabrication.

Forming ferroelectric polymer memories

An embodiment mitigates one or more of the limiting factors of fabricating polymer ferroelectric memory devices. For example, an embodiment reduces the degradation of the ferroelectric polymer due to the polymer's reaction with, and migration or diffusion of, adjacent metal electrode material. Further, the ferroelectric polymer is exposed to fewer potentially high temperature or high energy processes that may damage the polymer. An embodiment further incorporates an immobilized catalyst to improve the adhesion between adjacent layers, and particularly between the electrolessly plated electrodes and the ferroelectric polymer.

Polymer memory with adhesion layer containing an immobilized metal

A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.

Ferroelectric memory device with a conductive polymer layer and a method of formation

Methods for improving the net remnant polarization of a polymer memory cell are disclosed. In one embodiment, the polymer material is heated above the Curie temperature of the polymer material, and the domains of the polymer material are aligned with an externally applied electric field.

Method for increasing ferroelectric characteristics of polymer memory cells

Growing community of inventors

Portland, OR, United States of America

Ebrahim Andideh