International Business Machines Corporation

Eberhard Amann

Frank Haverkamp

Jan Kunigk

Thomas Huth

Juergen Saalmueller

Helga Hermann

Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Multi-chip initialization using a parallel firmware boot process

Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Integrated link calibration and multi-processor topology discovery

A method is provided to adjust time delays and sequence ordering of data channels in synchronous clocked bus systems. In particular, the invention relates to a method to re-synchronize data in respective channels which have a relative delay to each other caused by different path lengths, etc., on the way from sender to receiver. Still more specifically, the invention relates to an apparatus used to eliminate those delays in order to make data usable again on the receiver side. The method can be carried out using standard microprocessors without the need for special hardware implementations. Thus the use of costly and performance intensive ASICs and signal processors can be avoided.

Method and apparatus for adjustment of time delays in synchronous clocked bus systems

Method and apparatus are provided for re-synchronizing a group of B channels in an ISDN network using the BONDING Mode 1 specification. Re-synchronization is achieved without the need to first disconnect the affected group of B channels from the network. Thus, the reliability of the bonded channels is improved while maintaining a simpler architecture than those associated with BONDING Modes 2 and 3. The solution offers improved channel reliability, improved network performance and reduced network load when channel re-synchronization becomes necessary.

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Rottenburg, Germany

Eberhard Amann