International Business Machines Corporation

Ebenezer E Eshun

Douglas Duane Coolbaugh

Anthony K Stamper

Zhong-Xiang He

Robert Mark Rassel

Anil Kumar Chinthakindi

Timothy Joseph Dalton

Kunal Vaed

Jeffrey P Gambino

Daniel C Edelstein

William Joseph Murphy

Keith Edward Downes

Vidhya Ramachandran

Terence B Hook

Edmund Juris Sprogis

John Michael Cotte

Richard Paul Volant

Natalie Barbara Feilchenfeld

Kenneth Jay Stein

Matthew D Moon

Steven H Voldman

Jeffrey Bowman Johnson

Eric Jeffrey White

Jonghae Kim

Kevin Shawn Petrarca

Richard John Rassel

Daniel J Jaeger

Ronald Jay Bolam

Jean-Oliver Plouchart

Thomas A Wallner

Phung T Nguyen

John Edward Florkey

Sarah L Lane

Barbara Ann Waterhouse

Eric M Coker

Michael Lawrence Gautsch

Sarah L Grunow

Ping-Chuan Wang

Alvin Jose Joseph

Chandrasekharan Kothandaraman

Herbert Lei Ho

Hanyi Ding

Vincent James McGahay

Roger Allen Booth, Jr

Michael Joseph Zierak

Richard A Phelps

Deok-Kee Kim

Joseph Francis Shepard, Jr

Hongwen Yan

Dan Moy

John Matthew Safran

Ephrem G Gebreselasie

Kimball M Watson

Norman Whitelaw Robson

Heidi L Greer

Michael D Gordon

Michael L Zierak

A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

Method of making heat sink for integrated circuit devices

Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

Interconnect structures and design structures for a radiofrequency integrated circuit

A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

Method of forming MIM capacitor structure in FEOL

A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.

Bipolar transistor integrated with metal gate CMOS devices

Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Methods of fabricating passive element without planarizing and related semiconductor device

A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

Process for single and multiple level metal-insulator-metal integration with a single mask

A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, a dielectric block comprising one or more dielectric layers, a lower plate comprising one or more electrically conductive layer; and a spreader plate comprising one or more electrically conductive layers.

MIM capacitor and method of making same

An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.

Interdigitated vertical parallel capacitor

Interconnect structures, methods for fabricating interconnect structures, and design structures for a radiofrequency integrated circuit

A method of cooling a resistor is provided. The method includes forming a first electrical insulator having a high thermal conductivity in thermal contact with an electrically resistive pathway and forming a substrate adjacent the electrical insulator. The method further includes forming a first electrical conductor having a high thermal conductivity within the second substrate and in thermal contact with the electrical insulator.

Method of cooling a resistor

The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Method and structure for creation of a metal insulator metal capacitor

Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor

Method of forming bipolar transistor integrated with metal gate CMOS devices

MIM capacitor structure in FEOL and related method

Growing community of inventors

Essex Junction, VT, United States of America

Ebenezer E Eshun