Honeywell Information Systems Inc.

Earnest M Monahan

Garvin Wesley Patterson

Jaime Calle

John M Woods

William A Shelly

Marion G Porter

Jerome J Twibell

Edward F Weller, Iii

Robert J Garvey

George L Parris

Donald V Mills

An input/output system includes at least a pair of processing units and system interface apparatus for comparing the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus includes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the processing units is faulty. The system interface apparatus, following signal indications of a certain minimum confidence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables system operation to be continued with the good processing unit. To ensure reliable processing, both halves of the pair are tested when a miscompare cannot be related to an error condition associated with one of the pair notwithstanding the fact that the first processing unit tests well. Following reconfiguration, the operating system associated with the system provides periodic testing of the good processing unit, thereby ensuring that the system continues to operate reliably.

Input/output processing system utilizing locked processors

An input/output processing system comprises a number of modules including at least a pair of processing units connected to operate as a logical pair and a system interface unit having a number of ports. Each port connects to a different one of the modules for interconnecting pairs of modules for communication over a number of switching circuit networks included in the system interface unit. The system interface unit further includes control logic circuits for disconnecting each processor of the logical pair preventing the disconnected processing unit from communicating with other modules. The control logic circuits further include circuits which in response to special commands from a good processor are operative to condition via a special line, circuits in the disconnected processing unit to apply status signals representative of the contents of a control register to the system interface unit. The other circuits within the system interface unit in response to a further command condition certain switching circuit networks for loading the status signals into one of the registers included in the system interface unit for subsequent analysis by system routines.

Input/output maintenance access apparatus

An automatic reconfiguration hardware capability for automatically altering the local memory/processor configuration and reinitiating a bootload sequence in the event of a failure in the start-up phase of the input/output processor bootload. The automatic reconfiguration logic is enabled when a bootload request originates from the system console or the central system. Once a bootload request is initiated, all possible local memory/input-output processor (IOPP) configurations are attempted without further manual intervention. If no configuration is successful, a bootload error indication is presented at the I0P configuration panel.

Automatic reconfiguration apparatus for input/output processor

A dispatcher mechanism for assigning to a processor the highest priority peripheral having the highest priority request. In a data processing system having at least one processor, and a plurality of peripheral devices coupled to a system interface unit SIU utilized for communication between said processor and peripheral devices, and also having a plurality of processes competing for control of said processor, a priority interrupt mechanism determines the highest priority peripheral having the highest priority request and then provides an interrupt signal to the processor. A release instruction REL is used to exit the process. The dispatcher mechanism dispatches data to the processor upon request from the processor in order to give control of the processor to the highest priority request.

Apparatus for dispatching data of the highest priority process having

An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations. Each multiplexer unit includes a plurality of storage registers which are operatively coupled to the programmable interface associated therewith for receiving control information therefrom designating the priority to be given by the unit to the processing of different types of interrupt signals received from devices associated therewith in addition to information designating which one of a set of processing routines to be used in servicing the interrupt.

Programmable interface apparatus and method

Priority interrupt hardware monitors for the existence of, and determines the relative importance of requests to determine or attempt to determine when to interrupt an executing process on a processor. The processor may be interrupted only when the hardware determines that something more important needs to be done than what is being done by the currently executing process. Additionally, the processor may set interrupts for itself so that a portion of an executing process may be executed at a higher priority than that required for the remaining portion of the same process.

Priority interrupt mechanism

An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command sequences and a multiplexer unit which directly controls transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. The system interface unit which operatively provides connections between the different modules includes apparatus for generating steering codes defining the physical location of each module requiring service by another module of the system. The system interface unit appends information provided by the particular module generating a requesting request for attention to the steering code generated. The generation of steering code information by the system interface unit and the module included in such requests insures that only authorized accesses are made to the different modules during the input/output processing unit's execution of programs during the running of processes associated therewith.

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Phoenix, AZ, United States of America

Earnest M Monahan