Dell Products Inc.

Emc IP Holding Company LLC

Emc Corporation

Earl Medeiros

Ramesh Doddaiah

Owen Martin

Parmeshwr Prasad

Adnan Sahin

Peng Wu

Michael J Scharland

Rahul Deo Vishwakarma

Rong Yu

Malak Alshawabkeh

James Marriot Guyer

Jaeyoo Jung

Jason J Duquette

Peng Yin

Kaustubh S Sahasrabudhe

Mark D Moreau

Richard Trabing

Thomas Mackintosh

Venkata Khambam

A method is provided, comprising: obtaining a current wear metric value that is associated with at least one storage device; obtaining an expected wear metric value that corresponds to the current wear metric value; comparing the current wear metric value to the expected wear metric value; and decreasing a maximum power consumption limit of the storage device from a current level to a first level that is lower than the current level, the maximum power consumption limit of the storage device being decreased in response to detecting that the current wear metric value exceeds the expected wear metric value by a first predetermined amount.

Automated power limit write pacing to control NAND endurance

A method for use in a storage processor, comprising: generating or updating a cache metadata table that identifies a plurality of cache slots, for each of the plurality of cache slots, the cache metadata table including a different respective location identifier that indicates a location for that cache slot; receiving an I/O request that is associated with a logical block address; allocating a given one of the plurality of cache slots to the logical block address based on the respective location identifier that corresponds to the given cache slot; and executing the I/O request by using the given cache slot, wherein using the given cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command based on the memory address.

Location-based global cache tiering

Non-volatile Random Access Memory (NVR) on a storage system may be dynamically converted between use as temporary memory in a memory context and use as persistent memory in a storage context. NVR (e.g., embodied as DIMM) may be utilized in a hybrid capacity, where some of the NVR is used as memory and some of the NVR is used as storage, and where NVR memory is converted to memory as needed, dynamically as I/O is being processed using the NVR. A host system may be directly connected to an internal switching fabric of the data storage system without an intervening component of the storage system (e.g., a director) controlling access of the host system to the internal fabric or to the memory. The host system may provision and use the NVR as storage by directly communicating with the NVR over the internal fabric, for example, using RDMA.

Dynamic use of non-volatile ram as memory and storage on a storage system

The present disclosure relates to one or more memory management techniques. In embodiments, one or more regions of storage class memory (SCM) of a storage array is provisioned as expanded global memory. The one or more regions can correspond to SCM persistent cache memory regions. The storage array's global memory and expanded global memory can be used to execute one or more storage-related services connected to servicing (e.g., executing) an input/output (IO) operation.

Tiered persistent memory allocation

A Random Read Miss (RRM) distribution process monitors execution parameters of first, second, and third emulations of a storage engine, and distributes newly received read operations between the emulations. The RRM distribution process assigns newly received read operations to the first emulation, unless the CPU thread usage of the first emulation or the response time of the first emulation meet a first set of criteria. The RRM distribution process secondarily assigns newly received read operations to the second emulation, unless the CPU thread usage of the second emulation or the response time of the second emulation meet a second set of criteria. The RRM distribution process assigns all other newly received newly received read operations, that are not assigned to the first emulation or to the second emulation, to the third emulation. Distribution of read IOs between the emulations enables the storage engine to increase IOPs while minimizing response time.

Method and apparatus for distributing read operations between emulations in a storage engine

Mirrored volatile memory in a storage system is configured with a dual cast region of addresses. Buffers in the dual cast region are allocated for data associated with a received Write IO. A host IO device associates the dual cast addresses with the data. A switch or CPU complex recognizes the dual cast addresses associated with the data and, in response, creates and sends a first copy of the data to a first volatile memory mirror and creates and sends a second copy of the data to a second volatile memory mirror. The second copy may be sent via PCIe NTB between switches or CPU complexes.

Dual cast mirroring from host devices

A portion of the shared global memory of a storage array is allocated for write-only blocks. Writes to a same-block of a production device may be accumulated in the allocated portion of memory. Temporal sequencing may be associated with each accumulated version of the same-block. When idle processing resources become available, the oldest group of same-blocks may be consolidated based on the temporal sequencing. The consolidated block may then be destaged to cache slots or managed drives. A group of same-blocks may also be consolidated in response to a read command.

Fast small write forwarding with non-temporal cache memory

Determining storage of particular data in cache memory of a storage device includes using a first mechanism to determine when to remove the particular data from the cache memory and using a second mechanism, independent from the first mechanism, to inhibit the particular data from being stored in the cache memory independent of whether the first mechanism otherwise causes the particular data to be stored in the cache memory. The first mechanism may remove data from the cache memory that was least recently accessed. The second mechanism may be based, at least in part, on a prediction value of an expected benefit of storing the particular data in the cache memory. The prediction value may be determined based on input data corresponding to measured cache read hits (RH), cache write hits (WH), cache read misses (RM), cache write destage operations (WD), and prefetch reads (PR) for the particular data.

Optimizing cache performance with probabilistic model

A method includes: A. providing a substrate having a first surface and a second surface, the first surface being adapted for mounting an electronic device thereon; B. forming a grid of electrically conductive vias extending from a region proximate the first surface to a region proximate the second surface, each via being one of a signal via, a ground via and a power via; C. removing at least one of the vias to form a void between at least one ground via and at least one power via; and D. connecting each of the at least one ground via proximate the void to one of the at least one power vias proximate the void with a filter device proximate the second surface of the substrate.

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Fall River, MA, United States of America

Earl Medeiros