Intel Corporation

Earl J Wight

Theodore Zale Schoenborn

Michael W Leddige

Chaitanya Sreerama

Stephen H Hall, Jr

Jason A Mix

Olufemi B Oluwafemi

Nathaniel L Desimone

Duane M Heller

Paul G Huray

Maria F Pineda

Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream.

Crosstalk aware decoding for a data bus

A system and method consistent with the present disclosure includes determining a jitter tolerance of a particular lane of a communication link corresponding to each of a plurality of equalization coefficients. Further, determining a particular equalization coefficient of the plurality of equalization coefficients that provides a maximum jitter tolerance. Next, using the particular equalization coefficient for the particular lane of the communication link during operation based on determining the particular equalization coefficient which provides the maximum jitter tolerance.

Apparatus, system, and method for improving equalization with a software equalization algorithm

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Aloha, OR, United States of America

Earl J Wight