Semiconductor Components Industries, LLC

Motorola Corporation

Freescale Semiconductor,inc.

Earl D Fuchs

Sudhama C Shastri

Gordon M Grivna

David D Marreiro

Nicholas David Rizzo

Mark A Durlam

Jaynal Abedin Molla

Gregory W Grynkewich

Brian R Butcher

Kelly Wayne Kyler

Mark F Deherrera

Jeffrey H Baker

John J D'Urso

J Jack Ren

Yenting Wen

Herng-Der Chiou

Mark A Thomas

Ryan J Hurley

Emily M Linehan

Gary G Ehlenberger

In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

Method of forming a high capacitance diode

Method of forming a high capacitance diode and structure therefor

In one embodiment, a split well region of one conductivity type is formed in semiconductor substrate of an opposite conductivity type. The split well region forms one plate of a floating capacitor and an electrode of a transient voltage suppression device.

Semiconductor filter structure and method of manufacture

A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().

Cladded conductor for use in a magnetoelectronics device and method for fabricating the same

A diffusivity and a solubility of dopant atoms are increased within a semiconductor wafer (30). A portion (36) of the semiconductor wafer (30) is disrupted by a technique of ion implantation thereby forming a defect layer (36). A predeposition layer (37) is formed by placing the semiconductor wafer (30) in a predeposition furnace. The defect layer (36) has a large number of point defects in a semiconductor crystal lattice which accept dopant atoms in excess of their solid solubility limit. The point defects increase the diffusivity and solubility of the dopant atoms thereby increasing a junction depth and surface concentration in subsequent high temperature diffusion steps.

Method for doping a semiconductor wafer having a diffusivity enhancement

An improved method and structure for high voltage semiconductor devices capable of blocking voltages of the order of 1000 volts and greater is described. In a preferred embodiment, a blanket P layer is formed in an N.sup.- epi-layer on an N.sup.+ substrate. An annular groove is etched through the blanket P layer into the N.sup.- epi-layer. The bottom of the groove is doped N.sup.+ using the same mask as for the first groove etch. A second groove is formed inside of and partly overlapping the first groove and extending to a greater depth than the first groove, but not through the epi-layer. The second groove is filled with passivating material, metal electrodes are applied to the P.sup.+ region and the N.sup.+ substrate, and the devices separated at the N.sup.+ region lying outside the second groove in the bottom of the first groove. Excellent high voltage blocking characteristics are obtained with the same or fewer process steps and better yield.

Method of making high voltage semiconductor device

An improved method and structure for high voltage semiconductor devices capable of blocking voltages of the order of 1000 volts and greater is described. In a preferred embodiment, a blanket P layer is formed in an N.sup.- epi-layer on an N.sup.+ substrate. An annular groove is etched through the blanket P layer into the N.sup.- epi-layer. The bottom of the groove is doped N.sup.+ using the same mask as for the first groove etch. A second groove is formed inside of and partly overlapping the first groove and extending to a greater depth than the first groove, but not through the epi-layer. The second groove is fileld with passivating material, metal electrodes are applied to the P.sup.+ region and the N.sup.+ substrate, and the devices separated at the N.sup.+ region lying outside the second groove in the bottom of the first groove. Excellent high voltage blocking characteristics are obtained with the same or fewer process steps and better yield.

High voltage semiconductor device and method

Growing community of inventors

Phoenix, AZ, United States of America

Earl D Fuchs