Compaq Computer Corporation, Inc.

Earl C Reeves

Gary W Thome

Kameron H Ayati

David M Olson

A computer system, bus interface unit employing a memory controller, and method are presented for optimizing the bandwidth data, address, and control transfer rates across a memory bus coupled to an SDRAM system. The SDRAM system is partitioned such that one partition will undergo pre-charge or refresh in the interim between times in which another partition (or a pair of partitions) initiate a burst read. The burst read cycles coincide with an initial column address of the burst, and are spaced a number of cycles equal to the burst length. Proper spacing of the initial column address, or read request, relative to a non-read requested partition ensures data read from the activated partition will be placed on the memory data bus in seamless fashion. That is, there are no non-data transfers occurring between data burst cycles, even though refresh or pre-charge operations are performed on a non-read partition. Careful placement of the hidden refresh cycles encountered by one partition relative to read cycles on other partitions ensures the data flow resulting therefrom will be optimized to sustain peak bandwidth on a synchronous DRAM memory bus.

Apparatus and method for enhancing data transfer to or from a SDRAM system

A method and apparatus for designing a computer system which supports multiple processors of different types. A processor base board is separately connectable to a system board. The processor base board includes a number of connectors for receiving processor boards. The processor boards include a processor and, if necessary, a voltage regulator and voltage level converters. A right angle single edge contact connector is used on a Pentium II board to significantly reduce spacing requirements of adjacent processor boards. A conventional pin grid array type socket is used for a Pentium Pro processor board. A special mapping of bus request signals is disclosed for supporting four Pentium Pro processors or two Pentium II processors without requiring changes to the processor base board.

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Tomball, TX, United States of America

Earl C Reeves