Hewlett-Packard Company

Other

Hewlett-Packard Corporation

Earl C Herleikson

Richard A Baumgartner

Charles E Moore

William J Crilly, Jr

James M Lindauer

Thomas R Faulkner

A flexible ECG monitoring system including pace pulse detection. The monitoring system includes a potable monitor 102 that can be worn by a patient 120 or connected to a docking station 104. The portable monitor 102 includes an A/D converter 210, 208 and a digital signal processor 202. ECG signals are digitized and the digital signal processor derives a signal that is an estimate of the slope of the ECG signal. Pace pulses are detected by processing the slope signal, including use of a threshold that is dynamically updated based on the recent history of the slope signal. Detected pace pulses are removed prior to certain ECG filtering and reinserted following such filtering.

ECG pace pulse detection and processing

A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Serial processing circuits with serial chaining

Integrated circuit for physiological signal measurement

A high-accuracy QRS detector detects 'activity' on the ECG waveform. Activity results from a steep slope of one sense followed shortly thereafter by a steep slope of the opposite sense. Low-pass filtering activity and multiplying by 2.5 yields a noise threshold. An activity peak which rises above this threshold may be a QRS complex. The detector waits three-fourths the average R to R interval after detecting a peak to allow for greater peaks to be detected. If none are, the peak is confirmed if it is either at least half the magnitude of the previous peak, or if it occurs at least three-fourths the average R to R interval after the last detected peak. This high-accuracy detector may be coupled with a fast QRS detector by providing it with the peak values of the previous three detections. The fast detector will detect if the slope is greater than three-fourths the average of the previous three detections, greater than the noise threshold, and more than 160 ms has elapsed since its last detection.

QRS detector for defibrillator/monitor

Method and apparatus for removing baseline wander from an ECG signal. The ECG signal is filtered with a high-pass filter having a variable corner frequency. In response to finding low-frequency components in the output of the high-pass filter, its corner frequency is temporarily increased. The corner frequency may decrease according to a decay function or sensing the absence of a low-frequency component in the filter's output. The corner frequency may be decreased in response to sensing ECG activity.

Method and apparatus for accurately displaying an ECG signal

Signal processing circuits with digital programmability

Analog to digital converter with autoranging offset

In an adjacent channel measurement system, a desired channel signal and an adjacent channel signal are generated using a single signal generator. The output from this generator is modulated with a signal from an offset oscillator to produce a carrier and a sideband signal, one in each channel. The ratio of the carrier amplitude to the sideband amplitude is set by the system's modulation index, which is controlled by an audio attenuator on the output of the offset oscillator.

Adjacent channel selectivity signal generator system

A programmable low noise frequency modulated signal source including a voltage controlled oscillator (VCO) having a frequency locked loop (FLL) constituting a first feedback path and a phase lock loop (PLL) constituting a second feedback path is provided. The PLL includes a VCO, a programmable fractional-N frequency division network for changing the rational number by which the VCO output signal is frequency divided, a phase detector for comparing the phase of the VCO output signal with the phase of a reference signal and for producing an error signal for controllably adjusting the output frequency of the VCO. The FLL includes a delay line frequency discriminator, a loop amplifier and filter to provide a first feedback signal to the VCO to thereby reduce the phase noise on the VCO output signal. The frequency discriminator includes a first signal path having a frequency sensitive time delay network to provide a phase shift as a function of the VCO output signal frequency and a second signal path which includes a voltage controlled phase shifting network. The VCO tune voltage derived from the PLL phase detector is coupled to an input terminal at the voltage controlled phase shifting network. The tune voltage adjusts the phase difference between the two frequency discriminator signal paths to set the operating point of the FLL phase detector such that the VCO output signal will have a desired frequency. Since the PLL VCO tune signal is coupled to the control input of the voltage control phase shifting network the FLL phase detector operates without an offset voltage at its output. Low distortion frequency modulation of the (FM) VCO output signal is achieved by coupling an FM signal to the voltage controlled variable phase shift network.

Signal generator utilizing a combined phase locked and frequency locked

A low noise floor amplitude detector circuit utilizes a pair of semiconductor diodes connected between a radio frequency signal source and a terminating device that biases the diode at a conduction angle selected for maximum signal to noise ratio in the detector circuit. Optimum bias conditions and a low signal to noise ratio is achieved by using a conduction angle at each diode of 1.656 radians (approximately 67 degrees). This also results in matching of the radio frequency load impedance of the amplitude detector to the radio frequency impedance of a signal source.

High signal to noise ratio amplitude detector

A signal source which provides a carrier signal having a precisely set signal-to-noise ratio is provided. The carrier signal and its sideband noise components are attenuated below the equivalent thermal noise floor of an attenuator. The attenuated carrier signal and the equivalent thermal noise floor are then amplified in an amplifier having a known noise figure to produce a composite carrier signal having a usable power level and a precisely known signal-to-noise ratio. Since the equivalent thermal noise floor is a function only of temperature, the desired carrier signal-to-noise ratio may be set by setting the power level of the carrier signal and knowing the noise figure of the amplifier.

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Yamhill, OR, United States of America

Earl C Herleikson