Silicon Graphics, Incorporated

Mips Computer Systems, Inc.

Earl A Killian

Thomas J Riordan

Ashish B Dixit

Danny L Freitas

Larry B Weber

Mark I Himelstein

John L Hennessy

Paul S Ries

Edwin L Hudson

Todd C Mowry

A pipeline processor, when processing a branch instruction, initiates fetching of both the target and fall-through streams prior to execution of the branch instruction such that the number of pipeline cycles between completion of execution of the branch instruction and initiation of processing of the head instruction of the target or fall-through stream is less than the minimum number of pipeline cycles between fetching of an instruction and the execution of the instruction. At least one otherwise wasted pipeline cycle is saved by early instruction fetching and storing in a prefetch register. In some cases, two or more otherwise wasted cycles can be saved.

Method and apparatus for reducing delays following the execution of a

A TLB which has at least two page frame numbers (PFN) associated with each tag (Virtual Page Number) is provided. Thus, a match will produce two possible physical page frame numbers. The selection between these two is controlled by a bit provided directly from the virtual address, without translation. This bit is preferably the least significant bit of the virtual page number, or the first bit after the physical offset. This structure effectively doubles the capacity of the TLB without doubling the number of tags. Although the virtual space covered by each tag or VPN is necessarily restricted to two contiguous areas, the invention allows these two contiguous areas to be mapped to completely different regions of the physical address space. In addition to limiting the number of tags required, the number of comparators required is also similarly limited, with only the number of physical page frame numbers stored being required to double.

TLB with two physical pages per virtual tag

A method and computer program-product for converting a program designed to be executed on a computer system employing a first predefined memory order, such as the Big Endian architecture, to a program which is executable on a computer system employing a second predefined memory order, such as the Little Endian architecture. The method and computer program-product uses the fact that performing a logical operation on the lower two bits of a byte address in one architecture converts that byte address to the equivalent byte address in the other architecture. The method and computer program-product are implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and operating on the two least significant bits of the byte address with a logical operation to generate two complementary bits used to replace the two least significant bits of the byte address to generate a new byte address that corresponds with the other architecture.

System and method for obtaining correct byte addresses by using logical

A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended versions of m-bit entities, produce an N-bit result that may not correspond to the correct m-bit result, sign-extended to N bits. For these instructions compatibility requires that the instructions be further defined to guarantee a sign-extended result. This means that separate N-bit instructions corresponding to these m-bit instructions are needed. The support for up to an N-bit virtual address space is provided in part by widening the virtual address data paths. The extended architecture supports the m-bit architecture's addressing with minimal additional hardware. This is made possible by storing m-bit addresses as N-bit entities in sign-extended form and requiring that the results of address computations on these entities be in sign-extended form.

Backward-compatible computer architecture with extended word size and

A cache memory system includes a primary cache characterized by a virtual index and physical tags, and a secondary cache characterized by a physical index and physical tag. Thus, the cache system forms a hybrid of physical-cache and virtual-cache characteristics. Further, the secondary cache includes a primary index segment for each line of secondary cache. The primary index segment corresponds to a portion of the virtual address for the contents stored at the respective secondary-cache line. Further, primary cache is maintained as a subset of secondary cache. To maintain the primary cache in such a way, the primary index segment is used to generate an index into primary cache to identify each potential primary-cache block which may be a subset of a secondary-cache block to be changed. When a secondary-cache block is to be invalidated, flushed or overwritten, the corresponding primary-cache blocks are identified and invalidated. The primary index segment also serves as a virtual tag for assuring that at any given time primary cache stores no more than one valid block corresponding to the same physical locations. When a secondary-cache hit occurs in response to a secondary-cache physical tag check, the primary index segment is compared to a portion of the virtual address. If the segment does not match, then primary cache may already have a word stored which corresponds to the desired physical location. As a result, the corresponding block in primary cache is invalidated and the primary index segment in secondary cache is changed to the current virtual address segment.

Hybrid cache having physical-cache and virtual-cache characteristics and

A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte address in the other architecture. The conversion method and apparatus is implemented in hardware by setting a bit in a status register indicating a Big Endian or Little Endian architecture in conjunction with an XOR gate which couples the byte address to binary 3. The conversion method and apparatus is implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and XORing the two least significant bits of the byte address with a binary 3.

System for obtaining correct byte addresses by XOR-ING 2 LSB bits of

A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.

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Los Altos, CA, United States of America

Earl A Killian