Semitool, Inc.

Quality Microcircuits Corporation

Ramtron International Corporation

Other

Inmos Limited

Nippon Steel Semiconductor Corporation

Ramtron Corporation

Nmb Semiconductor Company, Ltd.

Applied Materials, Inc.

E Henry Stevens

Thomas Lee Ritzdorf

Lyndon W Graham

LinLin Chen

Curt T Dundas

Richard Allen Bailey

Thomas C Taylor

Richard Pfeiffer

Robert W Berner

Douglas Blaine Butler

Paul J McClure

Masahiro Maekawa

Christopher W Hill

Curt Dundas

A method for filling recessed microstructures at a surface of a microelectronic workpiece, such as a semiconductor wafer, with metallization is set forth. In accordance with the method, a metal layer is deposited into the microstructures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed microstructures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties. Various novel apparatus for executing unique annealing processes are also set forth.

Method for low temperature annealing of metallization micro-structures in the production of a microelectronic device

Method and apparatus for low-temperature annealing of metallization microstructures in the production of a microelectronic device

Method and apparatus for low temperature annealing of metallization micro-structure in the production of a microelectronic device

A process for providing one or more protected copper elements on a surface of a workpiece is set forth. In accordance with the process, a barrier layer is applied to the workpiece. If the barrier layer is not suitable as a seed layer for subsequent electroplating processes, a separate seed layer is applied over the surface of the barrier layer. One or more copper elements are then electroplated on selected portions of the seed layer or, if suitable, the barrier layer. If used, the seed layer is then substantially removed. At least a portion of a surface of the barrier layer is rendered unplatable while leaving the copper elements suitable for electroplating. A protective layer is then electroplated onto surfaces of the one or more copper elements.

Process and manufacturing tool architecture for use in the manufacture of one or more protected metallization structures on a workpiece

A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component is set forth. Generally stated, the process comprises the oxidation of at least a portion of the at least one thin-film layer and the etching of the oxidized thin-film layer using an etchant that selectively etches primarily the oxidized thin-film layer.

Process for etching thin-film layers of a workpiece used to form microelectronic circuits or components

Apparatus for low-temperature annealing of metallization microstructures in the production of a microelectronic device

An apparatus for application of a chemical process to a workpiece in which movement and precise location of the workpiece within the apparatus is accomplished by means of a single linear actuator and two locator components. A sequence of liquid solutions may be applied to a surface of the workpiece during processing, and a sequence of controlled atmospheres may be provided within a reaction chamber of the apparatus to thereby facilitate implementation of chemical processes that utilize both liquid-phase and gas-phase reactions in concert.

Apparatus for application of chemical process to a workpiece

Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece

Process for etching thin-film layers of a workpiece used to form microelectric circuits or components

A manufacturing tool configuration for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed. The tool configuration comprises a film deposition tool set, a pattern processing tool set, a wet processing tool set, and a dielectric processing tool set.

Process and manufacturing tool architecture for use in the manufacture

A manufacturing tool configuration for applying one or more levels of interconnect metallization to a generally planar dielectric surface of a workpiece with a minimal number of workpiece transfer operations between the tool sets is disclosed. The tool configuration comprises a film deposition tool set, a hard mask formation tool set, a hard mask etching tool set, a pattern processing tool set, a wet processing tool set, and a dielectric processing tool set. The film deposition tool set is used to deposit a conductive barrier layer exterior to the planar dielectric surface of the workpiece and a conductive seed layer exterior to the barrier layer. The hard mask formation tool set is used to form a hard mask dielectric layer exterior to the seed layer in accordance with one of the disclosed processes, and to form a still further hard mask dielectric layer exterior to the hard mask dielectric layer. In accordance with a first disclosed process, the pattern processing tool set is used to provide an interconnect line pattern over the hard mask dielectric layer and to provide a post pattern over interconnect line metallization formed using the interconnect line pattern. In accordance with a second disclosed process, the pattern processing tools set is used to provide a post pattern over the further hard mask dielectric layer so that the post pattern is ultimately formed in the further hard mask dielectric layer. The hard mask etching tool set is used to etch exposed regions of the hard mask dielectric layer after formation of the interconnect line pattern thereover and, in accordance with the second disclosed process, the exposed portions of the further hard mask dielectric layer after the formation of the post pattern thereover. The wet processing tool set performs at least the following wet processing operations: 1) applying copper metallization, using an electrochemical deposition process, into the interconnect line pattern and the post pattern formed by the pattern processing tool set, 2) removing material applied by the pattern processing tool set to form the interconnect line pattern and the post pattern, 3) removing the hard mask dielectric layer and, if necessary, the further hard mask dielectric layer, and 4) removing portions of the seed layer and the barrier layer that are not overlied by interconnect line metallization. The dielectric processing tool set is used to deposit a dielectric layer over the interconnect line metallization and post metallization and for etching the deposited dielectric layer to expose upper connection regions of the post metallization. In accordance with one embodiment of the tools set architecture, an inspections tools set is also employed to inspect the workpiece at intermediate stages of the processing.

Process architecture and manufacturing tool sets employing hard mask

A multi-region material structure and process for forming capacitors and interconnect lines for use with integrated circuits provides (1) capacitor first or bottom electrodes comprising a transition-metal nitride; (2) a capacitor dielectric comprising a transition-metal oxide; (3) capacitor second or top electrodes comprising a transition-metal nitride, a metal or multiple conductive layers; (4) one or more levels of interconnect lines; (5) electrical insulation between adjacent regions as required by the application; and (6) bonding between two regions when such bonding is required to achieve strong region-to-region adhesion or to achieve a region-to-region interface that has a low density of electrical defects. The process for forming the material structures involves formation of the capacitor dielectric on the first electrode surfaces by conversion of a conductive transition-metal nitride to an insulating transition-metal oxide and formation of low-defect-density interfaces between capacitor second electrodes and the capacitor dielectric.

Method of forming capacitors and interconnect lines

In fabricating a source/drain electrode of an integrated circuit transistor and a contact window for it: (1) establishing a structure with a window over the source/drain region next to a gate electrode and isolation structure; (2) establishing a dielectric layer covering the isolation structure, the window, and gate electrode; (3) implanting a moderate concentration of impurities into the source/drain region through said dielectric layer so that the moderate concentration region extends partially under the gate electrode; (4) removing the horizontal portions of the dielectric layer with an anisotropic etch thereby leaving the dielectric on vertical side walls; (5) establishing a region of titanium silicide over the moderately dosed source/drain region and establishing a titanium nitride layer over the isolation structure, windows, and gate electrode; (6) establishing a layer of silicon nitride over the titanium nitride layer; (7) implanting the substrate with a relatively heavier dose of ions through the silicon nitride, titanium nitride, and titanium silicide layers to create a heavier concentration source/drain region intersecting said moderate concentration region, where the heavy concentration region does not underlie the gate electrode; (8) patterning the silicon nitride layer; (9) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (10) adding thick interlevel dielectric over the patterned nitride layers; (11) opening windows over the electrodes; and (12) adding contact material in said windows.

Process for fabricating transistors using composite nitride structure

Capacitors and interconnect lines for use with integrated circuits

In fabricating a contact window to source/drain electrode next to a gate electrode of an integrated circuit: (1) establishing a structure with a window over the source/drain region next to the gate electrode; (2) establishing a region of titanium silicide over the source/drain electrode and establishing a titanium nitride layer over the window and gate electrode; (3) establishing a layer of silicon nitride over the titanium nitride layer; (4) patterning the silicon nitride layer; (5) using the patterned silicon nitride layer as a mask to pattern the titanium nitride layer; (6) adding another silicon nitride layer to seal the gate electrode where it is not protected by titanium nitride; (7) opening a window over the electrode by an anisotropic etch; (8) widening the window with an isotropic etch, using the silicon nitride and titanium nitride as a protective barrier; and (9) adding contact material in said windows.

Sealed self aligned contact process

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Colorado Springs, CO, United States of America

E Henry Stevens