Industrial Technology Research Institute

Dze-chaung Wang

Ruey-Liang Ma

Kun-Cheng Wu

Shi-Sheng Shang

Ching-Tang Chang

Chien-kuo Tien

George Shiang-Jyh Lai

A processor is provided with a decoder, a memory connected to the decoder and an execution stage connected to the decoder. The decoder receives each instruction. Each time the decoder receives an instruction, if the instruction contains a symbolic reference, the decoder determines whether or not the symbolic reference has been resolved into a numeric operand. If the symbolic reference has been resolved into a numeric operand, the memory retrieves, from a numeric reference table, a numeric operand to which the symbolic reference has been resolved. The execution stage then executes the instruction on the retrieved numeric operand in place of the symbolic reference. If the symbolic reference has not been resolved into a numeric operand, then the execution stage searches a data object, which relates each symbolic reference to a memory slot in which a corresponding numeric operand is stored, for a numeric reference relating the symbolic reference to a corresponding numeric operand. The memory then retrieves the numeric operand, that corresponds to the unresolved symbolic reference, from the memory slot indicated by the numeric reference of the data object. The memory stores the retrieved numeric operand in the numeric reference table maintained therein. The execution stage executes the instruction on the retrieved numeric operand in place of the symbolic reference of the instruction and indicates to the decoder that the symbolic reference is resolved. &ldquo;Resolved indications,&rdquo; which each indicates whether or not a specific, respective symbolic reference is resolved, can be stored in a numeric reference buffer and accessed using the instruction fetch address as an index. The numeric reference table can also be stored in the numeric reference buffer and accessed (indexed) the same way.

Intermediate instruction execution processor which resolves symbolic references without modifying intermediate instruction code

Methods and systems are disclosed for exploring instruction-level parallelism in superscalar processors by renaming stack entries. In a first embodiment, the stack renaming is implemented in a parallel structure that renames the instructions in parallel. In a second embodiment, the stack renaming is implemented in a serial structure that renames the instructions serially. In a third embodiment, the stack renaming is implemented in a combined parallel-serial structure that renames the instruction partially in parallel and partially in series.

Methods and systems of stack renaming for superscalar stack-based data

An improved method and apparatus for buffering and issuing instructions for use with superscalar microprocessors are disclosed. The method comprises the steps of: (a) obtaining an instruction buffer comprising a plurality of entries, each entry comprising a random access memory (RAM) portion and a content addressable memory (CAM) portion for storing result data and source operand tag, respectively, wherein the CAM portion also contains means for linking with an associated RAM portion and the result data contains an instruction; (b) providing a result bus capable of transmitting the result data and a result tag; (c) matching the result tag in the result bus with the source operand tag in the CAM, and writing the result data into the RAM portion of an entry if the result tag in the result bus matches the source operand tag of an associated CAM portion; and (d) issuing ready instructions and changing the source operand tag in a corresponding CAM in such a manner that the entry containing the CAM will be identified as an empty entry so as to all new instruction to be written thereto. Because instructions are stored in the RAM in an out-of-order, a linear systolic array is provided so as to keep the sequence of instructions in order. The linear systolic array, which can be easily compressed, allows the prioritization of instructions for issue among ready instructions, and the handling branch mis-prediction and faults to be implemented.

Growing community of inventors

Nantou, Taiwan

Dze-chaung Wang