Intel Corporation

Dz-ching (Roy) Ju

Guei-Yuan Lueh

Xiao-Feng Li

Zhaoqing Zhang

Yang Liu

Mark B Rosenbluth

Michael Kerby Chen

Aaron R Kunze

Sun C Chan

Lixia Liu

Ruiqi Lian

Junchao Zhang

Haibo (Jason) Lin

Guangrong Gao

A method and system to optimize throughput of executable program code are provided. The system comprises a profiler to receive a representation of a plurality of functions, an aggregator, and a mapper to map the plurality of aggregates to a plurality of processors. The aggregator may be configured to create an aggregate for each function from the plurality of functions thereby creating a plurality of aggregates, choose an optimization action between grouping and duplication based on the number of aggregates in the plurality of aggregates, the number of available processing elements (PEs), and execution time of each aggregate, and perform the chosen optimization action.

System and method for partitioning an application utilizing a throughput-driven aggregation and mapping approach

Techniques that may be utilized in a multiprocessor system are described. In one embodiment, one or more signals are generated to indicate that a breakpoint instruction is executed by one of the plurality of processors in the multiprocessor system. For example, a signal may be generated to indicate whether a processor is to be halted once it receives the a signal that indicates the breakpoint instruction. Other embodiments are also disclosed.

Multiprocessor breakpoint

There is provided a method and apparatus to reduce access to shared data storage. The apparatus analyzes a multithreaded application and generates metadata that is utilized to optimize the multithreaded application that executes on multiple processing elements.

Apparatus, systems and methods to reduce access to shared data storage

Operands may be assigned to physical registers within partitioned register banks by identifying possible candidate register banks for an operand. Prior to allocation of the operand to a candidate register bank, conflicts between candidate register banks, if any, may be identified and resolved.

Bank assignment for partitioned register banks

A method for an allocation of stacked registers for Intel's Itanium&#xae; processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.

Inter-procedural allocation of stacked registers for a processor

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Saratoga, CA, United States of America

Dz-ching (Roy) Ju