Omnivision Technologies, Inc.

Dyson Hsinchih Tai

Gang Chen

Duli Mao

Yin Qian

Yuanwei Zheng

Dajiang Yang

Chen-Wei Lu

Jin Li

Lindsay Alexander Grant

Ming Zhang

Vincent Venezia

Chih-Wei Hsiung

Chia-Chun Miao

Oray Orkun Cellek

Keiji Mabuchi

Cunyu Yang

Sohei Manabe

Bill Phan

Zhiqiang Lin

Howard E Rhodes

Xin Ru Wang

Sing-Chung Hu

Arvind Kumar

Qin Wang

Chao-Hung Lin

Siguang Ma

Dominic Massetti

Chia-Ying Liu

Wei Zheng

Kazufumi Watanabe

Cheng Zhao

Chun-Yung Ai

Guannan Chen

Qian Yin

Yi Ma

Boyd Fowler

Eric A G Webster

Johannes Solhusvik

Chin Poh Pang

Trygve Willassen

Xianmin Yi

Lequn Liu

Qingwei Shan

Bowei Zhang

Libo Weng

Wu-Zang Yang

Young Woo Jung

Zhenhong Fu

Philip John Cizdziel

Eric Webster

Tiejun Dai

Rui Wang

Rongsheng Yang

Kevin W Johnson

Boyang Zhang

Keh-Chiang Ku

Qingfei Chen

Jing Ye

Shao-Fan Kao

Chia-Jung Liu

Jiaming Xing

Jens Landgraf

Zhibin Xiong

Xianfu Cheng

Xi-Feng Gao

Jingming Yao

Hung Chih Chang

A pixel-array substrate includes a semiconductor substrate with a pixel array, a back surface, and a front surface, and a guard ring formed of a doped semiconductor, enclosing the pixel array, and extending into the semiconductor substrate from the front surface, the back surface forming a trench extending into the semiconductor substrate, the trench overlapping the guard ring. A method for reducing leakage current into a pixel-array includes doping a semiconductor substrate to form a guard ring that extends into the semiconductor substrate from a front surface, encloses a pixel array, excludes a periphery region, and resists a flow of electric current, and forming, into a back surface of the semiconductor substrate, a trench that penetrates into the back surface and overlaps the guard ring, the guard ring and the trench configured to resist the flow of electric current between the pixel array and the periphery region.

Electrical isolation in pixel-array substrates using combination of doped semiconductor guard rings and overlapping isolation trenches

An image sensor includes a substrate. An array of photodiodes is disposed in the substrate. A plurality of spacers is arranged in a spacer pattern. At least one spacer of the plurality of spacers has an aspect ratio of 18:1 or greater. A buffer layer is disposed between the substrate and the spacer pattern. An array of color filters is disposed in the spacer pattern.

Fully buried color filter array of image sensor

A semiconductor device that includes a metal pad buried in the semiconductor substrate that is electrically connected to a metal interconnection structure and electrically isolated from the semiconductor substrate. The semiconductor substrate forms an opening that extends from a back surface to the metal pad. A method for manufacturing a semiconductor device with buried metal pad including depositing, in a recess of a semiconductor substrate, a metal pad, isolating the pad from the substrate, electrically connecting the metal pad to the frontside of the substrate and connecting the metal pad to the backside of the substrate with an opening. A method for stabilizing through-silicon via connections in semiconductor device including electrically coupling a metal interconnection structure to a metal pad submerged in a semiconductor substrate and forming a through-silicon via into the semiconductor substrate that contacts the metal pad.

Semiconductor device with buried metal pad, and methods for manufacture

An image sensor pixel array comprises a plurality of image pixel units to gather image information and a plurality of phase detection auto-focus (PDAF) pixel units to gather phase information. Each of the PDAF pixel units includes two of first image sensor pixels covered by two micro-lenses, respectively. Each of the image pixel units includes four of second image sensor pixels adjacent to each other, wherein each of the second image sensor pixels is covered by an individual micro-lens. A coating layer is disposed on the micro-lenses and forms a flattened surface across the whole image sensor pixel array. A PDAF micro-lens is formed on the coating layer to cover the first image sensor pixels.

Image sensors with phase detection auto-focus pixels

A sensor includes a photodiode disposed in a semiconductor material to receive light and convert the light into charge, and a first floating diffusion coupled to the photodiode to receive the charge. A second floating diffusion is coupled to the photodiode to receive the charge, and a first transfer transistor is coupled to transfer the charge from the photodiode into the first floating diffusion. A second transfer transistor is coupled to transfer the charge from the photodiode into the second floating diffusion, and an inductor is coupled between a first gate terminal of the first transfer transistor and a second gate terminal of the second transfer transistor. The inductor, the first gate terminal, and the second gate terminal form a resonant circuit.

Sensor comprising gate modulation with inductor to form a resonant circuit

A flip-chip sample imaging device with self-aligning lid includes an image sensor chip, a fan-out substrate, and a lid. The image sensor chip includes (a) a pixel array sensitive to light incident on a first side of the image sensor chip and (b) first electrical contacts disposed on the first side and electrically connected to the pixel array. The fan-out substrate is disposed on the first side, is electrically connected to the first electrical contacts, forms an aperture over the pixel array to partly define a sample chamber over the pixel array, and forms a first surface facing away from the first side. The lid is disposed on the first surface of the fan-out substrate, facing away from the first side, to further define the chamber. The lid includes an inner portion protruding into the aperture to align the lid relative to the fan-out substrate.

Flip-chip sample imaging devices with self-aligning lid

An image sensor includes one or more photodiodes disposed in a semiconductor material to receive image light and generate image charge, and a floating diffusion to receive the image charge from the one or more photodiodes. One or more transfer transistors is coupled to transfer image charge in the one or more photodiodes to the floating diffusion, and a source follower transistor is coupled to amplify the image charge in the floating diffusion. The source follower includes a gate electrode (coupled to the floating diffusion), source and drain electrodes, and an active region disposed in the semiconductor material between the source and drain electrodes. A dielectric material is disposed between the gate electrode and the active region and has a first thickness and a second thickness. The second thickness is greater than the first thickness, and the second thickness is disposed closer to the drain electrode than the first thickness.

Image sensor having a source follower transistor with a multi-thickness gate dielectric

Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder bumps.

Interconnect layer contact and method for improved packaged integrated circuit reliability

An image sensor pixel array comprises a plurality of image pixel units to gather image information and a plurality of phase detection auto-focus (PDAF) pixel units to gather phase information. Each of the PDAF pixel units includes two of first image sensor pixels covered by a shared micro-lens. Each of the image pixel units includes four of second image sensor pixels adjacent to each other, wherein each of the second image sensor pixels is covered by an individual micro-lens. A coating layer is disposed on the micro-lenses and forms a flattened surface across the whole image sensor pixel array to receive incident light.

An image sensor pixel array comprises a center region and two parallel edge regions, wherein the center region is between the two parallel edge regions. The center region comprises a plurality of image pixels disposed along first sub-array of rows and columns, wherein each of the plurality of image pixels comprises a first micro-lens (ML) formed at an offset position above a first light receiving element as a countermeasure for shortening of exit pupil distance of the image pixel in the center region, and each of the two parallel edge regions comprises a plurality of phase detection auto-focus (PDAF) pixels disposed along second sub-array of rows and columns, wherein each of the plurality of PDAF pixels comprises a second micro-lens (ML) formed at an alignment position above a second light receiving element; and at least one of the PDAF pixels is located at a distance away from center of the edge region to receive incident light along an injection tilt angle.

Image sensors with phase detection auto focus pixels

A liquid crystal on silicon (LCOS) panel comprises: a silicon substrate having silicon circuit within the silicon substrate; a plurality of metal electrodes disposed on the silicon substrate, where the plurality of metal electrodes are periodically formed on the silicon substrate; a dielectric material disposed in and filling gaps between adjacent metal electrodes; and an oxide layer disposed on the plurality of metal electrodes and the dielectric material in the gaps between adjacent metal electrodes; where the refractive index of the dielectric material is higher than the refractive index of the oxide layer.

Liquid crystal on silicon panel having less diffraction

A reflective semiconductor device includes integrated circuitry disposed in a semiconductor layer. A first plurality of mirrors is formed in a mirror layer over the semiconductor layer, and each of the first plurality of mirrors is spaced apart from one another by at least a uniform width. A thin dielectric film layer covers sidewalls of the first plurality of mirrors and the semiconductor layer in the regions between the spaced apart first plurality of mirrors. A second plurality of mirrors are formed in the mirror layer between the thin dielectric film layer covered sidewalls of the first plurality of mirrors and over the thin dielectric film layer covering the semiconductor layer. Each one of the first and second plurality of mirrors has the uniform width, and is coupled to the integrated circuitry disposed in the semiconductor layer.

Liquid crystal on silicon device mirror metal process

An image sensor pixel includes a photodiode disposed in a semiconductor material to generate image charge in response to light incident on a backside of the semiconductor material, and a pinning layer disposed in the semiconducting material and coupled to the photodiode. The pixel also includes a vertical overflow drain disposed in the semiconductor material and coupled to the pinning layer such that the pinning layer is disposed between the vertical overflow drain and the photodiode. A floating diffusion disposed in the semiconductor material proximate to the photodiode, and a vertical transfer transistor is disposed in part in the semiconductor material and coupled to the photodiode to transfer the image charge from the photodiode to the floating diffusion in response to a transfer signal applied to the gate terminal of the vertical transfer transistor.

Vertical overflow drain combined with vertical transistor

A pixel array for use in a high dynamic range image sensor includes a plurality of pixels arranged in a plurality of rows and columns in the pixel array. Each one of the pixels includes a linear subpixel and a log subpixel disposed in a semiconductor material. The linear subpixel is coupled to generate a linear output signal having a linear response, and the log subpixel is coupled to generate a log output signal having a logarithmic response in response to the incident light. A bitline is coupled to the linear subpixel and to the log subpixel to receive the linear output signal and the log output signal. The bitline is one of a plurality of bitlines coupled to the plurality of pixels. Each one of the plurality of bitlines is coupled to a corresponding grouping of the plurality of pixels.

Linear-logarithmic image sensor

Growing community of inventors

San Jose, CA, United States of America

Dyson Hsinchih Tai