At&t Information Systems Inc.

At&t Bell Labs

Dwight W Kohs

Douglas A Spencer

John S Helton

Philip W Hartmann

Garry V Turnbow

Edward J Bortolini

A control circuit for receiving clock signals from duplicated sources, such as a pair of Time Slot Interchanges (TSI) and for normally extending the clock signal of the on-line source to clock signal utilization devices, such as digital port boards. The control circuit contains circuitry which ensures that no spurious pulses are applied to the port boards when the TSIs interchange their on-line/off-line status.

Glitchless clock signal control circuit for a duplicated system

The subject parity circuit generates a single parity bit for a prescribed DATA SET. The DATA SET comprises n bytes which are simultaneously transmitted to the parity circuit over n data transmission leads. The n bytes are simultaneously combined bit by bit to determine whether an odd or even number of bits have been received. A cummulative sum is determined, and the single parity bit is generated with the receipt of the last n bits of the DATA SET.

Single parity bit generation circuit

A PCM switching system requires the assignment of either one or two time slots of a pair of time slots to a port circuit depending upon the type of service (voice only or voice plus data) each port circuit provides. Common resources normally assign a pair of time slots to each port circuit. This wastes time slots when the port circuit is used in a manner (voice only service) that requires only a single time slot. The disclosed arrangement eliminates the wasting of time slots by permitting the on-site reconfiguring of the system resources so that, when desired, only a single time slot can be assigned to a port circuit. This is accomplished by the removal of a first type of carrier control board that controls time slot distribution and by the substitution therefore of a second type of control board that applies the first time slot of a pair to its normally assigned port circuit and applies the second time slot of the same pair to another port circuit on the same carrier that also only requires a single time slot. This permits a given system to be configured initially in a first mode and then be subsequently reconfigured on-site so the port circuits of a carrier can each be assigned either one or two time slots. This arrangement avoids the wasting of time slots or costly on-site modifications as service needs change.

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Broomfield, CO, United States of America

Dwight W Kohs