Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Compaq Computer Corporation, Inc.

Compaq Information Technologies Group, L.p.

Hewlett-packard Development, L.p.

Dwight L Barron

Jeffrey R Hilland

Paul A Santeler

Gerald K Kleyn

Paolo Faraboschi

Jeffrey Clifford Mogul

Michael R Krause

E David Neufeld

Norman Paul Jouppi

Paul R Culley

Sheng Li

Paul T Congdon

Kevin Mark Jones

Jonathan Bradshaw

Sompong Paul Olarig

Renato John Recio

Kevin B Leigh

Parthasarathy Ranganathan

Michael F Angelo

Terrel L Morris

Dejan S Milojicic

Michael S Schlansker

Siamak Tavallaei

Melvin K Benedict

Gregory Francis Pfister

Vanish Talwar

Jean Tourrilhes

David J Garcia

Andrew Brown

Doe Hyun Yoon

Luis E Luciani, Jr

Praveen Yalagandula

Chanh V Hua

Jayaram Mudigonda

Mitchel E Wright

Mark W Bradley

Joe Perry Cowan

Stephen G Low

David M Burckhartt

Mallikarjun Chadalapaka

Guodong Zhang

Prashant Modi

Kathryn Hampton

Yiu Yip

James G Wendt

Ambitabha Biswas

Wm Caldwell Crosswy

David W Abmayr

Harvey M Rosenblum

Andrew L Fisher

Managing multiple cartridges that are electrically coupled together includes obtaining general purpose command instructions from a chassis with a cartridge where the cartridge has a unique application and is connected to the chassis and further operating the unique application based on the general purpose command instructions.

Managing multiple cartridges that are electrically coupled together

In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

Memory controller with memory resource memory management

A network switch for implementing a Software Defined Network can include one or more memory resources storing a flow table and including a buffer. The network switch can receive and analyze data packets to generate a lookup key for each respective data packet. Using the lookup key, the network switch can perform a lookup in the flow table to determine a rule number for the respective data packet. Based on the rule number, the network switch can generate an event record for the respective data packet, and store the event record in a block of the buffer. When the block is full, the network switch can stream a set of event records from the buffer to a processing resource to enable the processing resource to update counter tables, external to the network switch, to implement the Software Defined Network.

Implementing a software defined network based on event records

A printed circuit board with a two-dimensional torus topology provided herein. The printed circuit board includes an array of board connectors, an input port and an output port, and a set of interconnections. Each board connector of the array of board connectors is formed to receive an electronic connector. The input port and the output port are formed on each board connector to provide an identical trace routing direction. The set of interconnections are formed to connect each board connector to another board connector. The signal path between each of the interconnections has a length less than a distance between a first board connector and a last board connector in the array of board connectors.

Two-dimensional torus topology

According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.

Memory network to route memory traffic and I/O traffic

According to an example, a resiliency group for a memory node in a memory network can provide error correction for a memory access in the memory node. The memory access may be received from a main memory controller of a processor connected to the memory network. The memory access may be executed by a memory controller of the memory node.

Memory node error correction

Each of a plurality of data packets that is received on a network switch can be associated with a corresponding event record that identifies one or more flow table rules for that data packet. A plurality of event records, which individually can correspond to one or more of the data packets, is transmitted to a programmable resource for use in controlling a Software Defined Network.

Implementing a software defined network using event records that are transmitted from a network switch

Connectors of a first removable modular optical connection assembly, having a first predefined arrangement of optical signal conduits, are connected to respective connectors on a support structure that are optically connected to corresponding devices. The first modular optical connection assembly is replaceable with a second modular optical connection assembly having a second, different predefined arrangement of optical signal conduits, to change a topology of a network.

Replaceable modular optical connection assembly

Example embodiments relate to autonomous metric tracking and adjustment. In some examples, a computing node may include a processor to run a main operating system and an application that runs on top of the main operating system. The computing node may include a hardware-level controller that dynamically adjusts individual hardware components of the computing node via control signals that do not pass through the main operating system. The adjustments may be based on a target metric from a scheduling service external to the computing node and individual performance metrics from the computing node.

Autonomous metric tracking and adjustment

A hardware enablement apparatus includes a processor, and a communications interface configured for writing license data to one or more data registers and for using the license data to selectively enable, under control of the processor, hardware features associated with the data registers, at least one of the data registers being implemented in non-volatile memory.

Hardware enablement using an interface

Example management processors, methods and articles of manufacture are disclosed. A disclosed example management processor includes a network card interface to communicatively couple the management processor to an operating environment, and a request processor to forward a received external management request to the operating environment via the network card interface, and to combine response information received from the operating environment with response information generated at the management processor.

Management processors, methods and articles of manufacture

A method of enforcing software license protection in a computer system comprising; morphing the data prior to distribution, resulting in morphed data; wherein morphing of data is accomplished by applying a reversible morphing algorithm to modify data, wherein said reversible morphing algorithm is uniquely seeded and/or controlled with control information.

Method and apparatus for enforcement of software licence protection

Growing community of inventors

Houston, TX, United States of America

Dwight L Barron