Advanced Micro Devices Corporation

Fujitsu Corporation

Dwight K Elvey

Someshwar Gatty

Emerson S Fang

Sanjeev K Maheshwari

Meei-Ling Chiang

Thomas A Clouqueur

Paul Wong

Joseph R Siegel

Kevin M Gillespie

Harry R Fair

Kamran Zarrineh

Ting-Yu Kuo

Mark O Porter

An integrated circuit device includes a plurality of flip flops configured into a scan chain. The plurality of flip flops includes at least flip flop of a first type and at least one flip flop of a second type. A method includes generating a first scan clock signal for loading scan data into at least one flip flop of a first type, generating a second scan clock signal and a third scan clock signal for loading the scan data into at least one flip flop of a second type, and loading a test pattern into a scan chain defined by the at least flip flop of the first type and the at least one flip flop of the second type responsive to the first, second, and third scan clock signals.

Method and apparatus for providing clock signals for a scan chain

A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.

Preventing A-B-A race in a latch-based device

A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.

Fault tolerant scannable glitch latch

An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.

Test techniques for a delay-locked loop receiver interface

Various embodiments of methods and systems for simultaneously testing multiple cores included in an integrated circuit are disclosed. In one embodiment, an integrated circuit may include two or more logic cores. The IC may also include structural scan test hardware coupled to the cores. This structural scan test hardware may be capable of inputting scan test vector data into scan registers associated with each of the logic cores, simultaneously executing a scan test on the logic cores included in the IC, and outputting the results of the scan tests for multiple cores to automated test equipment (ATE) simultaneously. In one embodiment, elements of the results of testing for multiple cores may be interleaved on a single output line such that an element of test result data from each core is present on an input channel to the ATE during each strobe window.

Simultaneous core testing in multi-core integrated circuits

The initialization process and structure of the system ensure that during loading of random data a 1-hot condition is maintained to the 1-hot multiplexer so as to prevent contention or a high current state. The present invention further improves observability of intermediate stages by preventing random data feeding of the state elements in scan chains that cannot tolerate random data. A scan chain having only scan registers that can receive random data is referred to as a LBIST Random Scan Chain (LRSC) and a scan chain having one or more scan registers that cannot tolerate and cannot receive random data is referred to as a &ldquo;LBIST Non-random Scan Chain&rdquo; (LNSC). A PRPG generates random data having a plurality of bit values to the LRSCs which is then passed to a multiple input shift register (MISR). The LNSCs do not receive random data from the PRPG but instead receive bit values from another scan chain. Before feeding bit values into a LNSC, the bit values are feed into a decoder and the LNSCs feed bit values reflecting test responses into the MISR. The system may further include recirculation lines in electrical communication with a LNSC to recirculate original bit values back into the LNSC.

Growing community of inventors

Santa Cruz, CA, United States of America

Dwight K Elvey