Hewlett-packard Development Company, L.P.

Compaq Computer Corporation, Inc.

Hewlett Packard Enterprise Development LP

Compaq Information Technologies Group, L.p.

Dwight D Riley

Christopher J Pettey

David J Maguire

James R Edwards

Hubert E Brinkmann

Paul V Brownell

David L Matthews

Montgomery C McGraw

Thomas R Seeman

James Xuan Dinh

Sompong Paul Olarig

Joseph Foster

Robert A Lester

Jeffrey C Stevens

Kenneth T Chin

Gregory N Santos

Christopher C Wanner

Brian S Hausauer

Thierry Fevrier

Bassam N Elkhoury

Hahn Norden

John Norton

Michael L Chan

Alan L Goodrum

Robert C Elliott

Kenneth A Jansen

Ronald Timothy Horan

Scott P Faasse

Shiva R Dasari

Chris Pettey

Hubert E Brinkmann, Jr

Robert W Noller

An apparatus in a first computing device is provided. During operation, the apparatus can present, to a processor of the first computing device, a virtual interface switch (VIS) coupled to an interface port of the processor. The apparatus can present to the processor that a target device, which is reachable via a remote apparatus of a second computing device, is coupled to the VIS. The apparatuses can be coupled via at least a first fabric and a second fabric. A respective fabric may facilitate communication based on a fabric switching protocol. The apparatus can obtain a set of packets, which can be issued from the interface port via the VIS and directed to the target device. The apparatus can then forward, to the remote apparatus, a first subset of the set of packets via the first fabric and a second subset of the set of packets via the second fabric.

Method and system for facilitating high availability in a multi-fabric system

Composable computing architectures with an interconnection fabric to provide high availability and fault tolerance are described. An interconnection fabric routes packets between compute resources, memory resources, and input/output (I/O) resources. A fabric manager is coupled with the interconnection fabric to receive an I/O or memory requirement for a compute workload for a host device, and to map individual I/O or memory resources from the plurality of I/O resources to individual compute resources from the plurality of compute resource and to dynamically map individual I/O resources from the plurality of I/O resources based on received resource requests.

Flexible high-availability computing with parallel configurable fabrics

A process includes enforcing compliance of a compute appliance to a reference operating state for the compute appliance. The compute appliance is part of a cloud-based computing system. Enforcing compliance with the reference operating state includes, responsive to a startup of the compute appliance, the compute appliance determining an actual compute state of the compute appliance. The actual compute state includes an actual physical topology placement of a hardware component of the compute appliance. Determining the actual compute state includes determining the physical topology placement of the hardware component. Enforcing compliance with the reference operating state includes verifying whether the actual compute state complies with the reference compute state. The verification includes comparing the actual compute state to the reference compute state. Enforcing compliance with the reference operating state includes, responsive to a result of the verification, controlling whether the compute appliance is part of the cloud-based computing system.

Enforcing reference operating state compliance for cloud computing-based compute appliances

A supervisory service of a node that includes a smart input/output (I/O) peripheral is extended into a cloud operator domain that is associated with the smart I/O peripheral. The supervisory service determines a state of a ready state indicator that is provided by the smart I/O peripheral. Based on the state, the supervisory service performs at least one of regulating an availability of an instance of an application operating environment of the node or determining whether the smart I/O peripheral is ready to be configured by the supervisory service.

Extending supervisory services into trusted cloud operator domains

In exemplary aspects described herein, system memory is secured using protected memory regions. Portions of a system memory are assigned to endpoint devices, such as peripheral component interconnect express (PCIe) compliant devices. The portions of the system memory can include protected memory regions. The protected memory regions of the system memory assigned to each of the endpoint devices are configured to control access thereto using device identifiers and/or process identifiers, such as a process address space ID (PASID). When a transaction request is received by a device, the memory included in that request is used to determine whether it corresponds to a protected memory region. If so, the transaction request is executed if the identifiers in the request match the identifiers for which access is allowed to that protected memory region.

Securing transactions involving protected memory regions having different permission levels

In some examples, a modular server includes an auxiliary power source and an auxiliary power system. The auxiliary power system includes a battery terminal to electrically couple to the auxiliary power source. The auxiliary power system further includes power terminals. Each power terminal is electrically coupled to a respective resource received within a modular server enclosure. The auxiliary power system further includes a power circuitry electrically coupled to the battery terminal and to each of the power terminals. The auxiliary power system also includes security circuitries. Each security circuitry corresponds to a respective resource received within a modular server enclosure. The auxiliary power source supplies power to the plurality of security circuitries.

Power circuitry for security circuitry

According to an example, a dual-port non-volatile dual in-line memory module (NVDIMM) includes a first port to provide a central processing unit (CPU) with access to universal memory of the dual-port NVDIMM and a second port to provide an external NVDIMM manager circuit with access to the universal memory of the dual-port NVDIMM. Accordingly, a media controller of the dual-port NVDIMM may store data received from the CPU through the first port in the universal memory, control dual-port settings received from the CPU, and transmit the stored data to the NVDIMM manager circuit through the second port of the dual-port NVDIMM.

Dual-port non-volatile dual in-line memory modules

According to an example, data may be replicated using a dual-port nonvolatile dual in-line memory module (NVDIMM). A processor may request, through a first port of the dual-port NVDIMM, to store data to universal memory of the dual-port NVDIMM and to commit the data to remote storage according to a high-availability storage capability of the dual-port NVDIMM. The process may then receive a notification from the dual-port NVDIMM that the data has been transparently committed to the remote storage through a second port of the dual-port NVDIMM.

Replicating data using dual-port non-volatile dual in-line memory modules

Embodiments of the present invention are directed to methods for virtualizing interrupt modes on behalf of interrupt-generating devices, including I/O-device controllers, so that newer interrupt-generating devices that lack older interrupt modes can be used in systems that continue to rely on older interrupt modes. In one embodiment of the present invention, a PCIe switch or PCIe-based host bridge is modified, or a new component introduced, to provide an interrupt-mode virtualizing function, or virtual interrupt-mode interface, that provides a virtual interrupt mode on behalf of interrupt-generating devices, such as I/O-device controllers, to operating systems, BIOS layers, and other components that communicate with the I/O-device controllers.

Virtual-interrupt-mode interface and method for virtualizing an interrupt mode

In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.

Presenting multi-function devices behind a switch hierarchy as a single function device

A hardware device interface supporting transaction authentication is described herein. At least some illustrative embodiments include a device, including an interconnect interface, and processing logic (coupled to the bus interface) that provides access to a plurality of functions of the device through the interconnect interface. A first transaction received by the device, and associated with a function of the plurality of functions, causes a request identifier within the first transaction to be assigned to the function. Access to the function is denied if a request identifier of a second transaction, subsequent to the first transaction, does not match the request identifier assigned to the function.

Configuration and association of a supervisory virtual device function to a privileged entity

A system and method for remote direct memory access over a network switch fabric. Some illustrative embodiments may include a system comprising a first system node, a direct memory access (DMA) controller, a second system node, and a network switch fabric coupling together the first and second system nodes (the network switch fabric comprises a rooted hierarchical bus). The DMA controller is configured to perform a DMA transfer of data between the first and second system nodes across the network switch fabric. The data is formatted as one or more remote DMA (RDMA) protocol messages that are routed across the network switch fabric based on a bus end-device identifier corresponding to the second system node.

System and method for remote direct memory access over a network switch fabric

Systems and methods of sharing legacy devices in a multi-host environment are disclosed. An exemplary method for sharing legacy devices in a multi-host environment includes receiving device information from a legacy device, the device information identifying a target within a virtual machine. The method also includes encapsulating the device information into a corresponding bus transaction for a network switch fabric. The method also includes routing the bus transaction over the network switch fabric in the virtual machine to a host within the virtual machine.

Sharing legacy devices in a multi-host environment

An apparatus and a method for setting a primary port on a PCI multi-port bridge. More specifically, there is provided a method that comprises detecting a configuration signal at the PCI multi-port bridge and automatically setting the primary port on the PCI multi-port bridge based on the configuration signal. A system for implementing the method is also provided.

Growing community of inventors

Houston, TX, United States of America

Dwight D Riley