At+t Corp.

At&t Bell Laboratories

Synopsys, Inc.

Dwight D Hill

Barry K Britton

William A Oswald

Satish Raj

Chi-Hung Wang

Dennis Ding

A hybrid clock distribution system uses a distribution fabric to distribute clock signals across longer physical distances and local sub-distribution networks to distribute clock signals more locally and to implement logic functions such as clock gating. A set of tap drivers connect the distribution fabric to the sub-distribution networks. A design tool automatically generates and places the set of tap drivers.

Automatic tap driver generation in a hybrid clock distribution system

A tightloop method of timing driven placement. The present invention interleaves timing analyses and updates net weight based on the timing analyses as part of the cell location refinement processes of a placement algorithm. Thereby, the placement algorithm is augmented to factor in timing information such that the final placement is effective from overlap, net length, and timing perspectives.

Tightloop method of timing driven placement

A method and system for high speed detailed placement of cells within an integrated circuit design. The novel detailed placement system receives a set of cells of an integrated circuit design where the cells have undergone coarse placement. Cells have variable width but the same height (or vice-versa). The cells are each assigned an initial coordinate position, e.g., using floating point precision values. During detailed placement, the cell coordinates are assigned to x-axis and y-axis grid lines. The detailed placement process sorts the cells based on their coordinates along a first axis, e.g., their x-axis coordinates; sort order dictates cell placement order. In one embodiment, sort order preference is given to the wider cells. For a given cell, placement is performed by scanning through the rows of the substrate and selecting the left-most positioned vacant site of each row as a candidate site for placement. A site is vacant if it does not contain a previously placed cell. Of the candidate sites, a valid site having the lowest cost (e.g., the nearest site) is selected for the cell. Some candidate sites are invalid due to the presence of obstructions or incompatible metal layers. A candidate site can also be invalid if it lies too far to the left of the cell, based on a left factor. Placement from left to right along the rows continues in this manner until all cells are placed. Alternatively, the process could run right to left, down to up or up to down.

Method and system for high speed detailed placement of cells within an integrated circuit design

A system and method for placement of elements within an integrated circuit design using a spanning tree model and a quadratic optimization based placement. The system utilizes a conjugate-gradient quadratic formula based placement system (e.g., GORDIAN) which inputs an integrated circuit design in a netlist form and generates a connectivity matrix for each multi-pin net within the design. The quadratic placement system performs global optimization using a conjugate gradient solution to minimize wire lengths of cells in nets. Partitioning is also performed. The system and method herein utilizes a clique model of a multi-pin net to generate first connectivity matrices for the multi-pin nets which are run through the global optimization processes. This first run provides a rough placement of the elements of the multi-pin nets. A spanning tree process is then run on the initial cell placement and subsequent connectivity matrices are constructed using the spanning tree model, not the clique model for multi-pin nets within a defined size range. Although biased toward the initial placement, the overall placement process as described herein is more physically realistic and efficient using the spanning tree model which requires much less data for storage and processing thus allowing faster convergence. A placed netlist is the product.

Method and system for placing cells using quadratic placement and a

Providing low-skew clock signals to a Field Programmable Gate Array (FPGA) chip normally requires devoting a certain number of bondpads to that purpose. However, that limits the number of clocks that may be applied, and may also limit which bondpads can be used for that purpose. In the present invention, any input/output bondpad may be used to supply a low-skew clock, or other global type signal, to one or more of the Programmable Function Units (PFUs). This is accomplished by using a criss-crossed grid of parallel conductor groups. Any of the conductors may be supplied by a clock from a bondpad or alternatively driven directly from a PFU, thereby allowing the distribution of internally-generated clocks. To facilitate programmable interconnects between the horizontal and vertical conductors, the outer conductor in a group crosses over the others at defined intervals, to thereby become the inner conductor. In this manner, each cell may drive a subset of the conductors in a group, thereby reducing the number of drivers needed. This allows all the buffer and conductor topologies to be identical for each cell, which significantly aids in the computer-aided design of the FPGA, as well as simplifying its programming.

Low-skew signal routing in a programmable array

A field programmable gate array (FPGA) includes a distributed switch matrix for programmably connecting the various routing conductors. The distributed switch matrix comprises groups of additional conductors, referred to as 'Switching R-nodes'. The Switching R-nodes programmably connect selected ones of the (e.g, horizontal) routing conductors to other selected ones of the (e.g., vertical) routing conductors. In this manner, the direct connection between the routing conductors may be avoided, allowing for a reduced number of programmable interconnect devices. In one preferred embodiment, a nibble-mode architecture is used, wherein four data conductors are provided for each group of routing conductors, with other multiples-of-four data conductors also being advantageous.

FPGA with distributed switch matrix

In accordance with the present invention, a field programmable gate array includes at least one programmable function unit. The programmable function unit has first and second logic circuits, each providing an output, and first and second output drivers, each having an input. The input of each output driver is adapted to be selectively coupled to the output of either of the logic circuits. A programmable interconnection is provided to selectively couple the input of the two output drivers to the output of a selective one of the logic circuits.

FPGA having PFU with programmable output driver inputs

A field programmable gate array that includes a dedicated path that directly connects an I/O pad to a selected register in the array of programmable function units. For example, a direct connection (i.e., without a configurable interconnect point) is provided from an I/O pad, through an input driver, to the input of a selected register in a given PFU. Either this same path, or alternatively a different path, may be used to directly connect a register output from a given PFU to an I/O pad, through an output driver. This technique avoids the need for special I/O registers in the programmable input/output cells, thereby increasing the flexibility of use and ease of design of the FPGA.

Field programmable gate array with direct input/output connection

A field configurable function element offers multi-function use of memory cells by organizing the cells in memory banks and by providing internal configurable interconnections of the memory banks. A versatile logic function configuration is obtained by storing the truth table of the desired logic functions in the memory cells. An arithmetic functions configuration is obtained by internally interconnecting the memory cells. A read/write memory function configuration is obtained by adding write address decoding, write enablement capability and input data leads. The configuration permits a parallel writing and reading of the memory cells, thereby effectuating a two-port memory operation. An added set of latches connected to the configurable function element and a configurable routing network connected to the inputs of the configurable function element, to the output of the configurable function element and to the output of the latches, form a powerful device that can be easily configured to any one of the three primary modes (logic, arithmetic and memory). A generalized routing fabric coupled to the routing network provides for configurable connections to other configurable function devices. To minimize the load that such a device may present to the routing fabric because of the various configurable interconnections that it can effect, the input leads from the routing fabric to the routing network in configurable function device are all multiplexed to one, or a few contact points, via an intermediate level of routing.

Fully configurable versatile field programmable function element

A field programmable array of application circuitry (C1, C2, . . .) is programmed (or reprogrammed) by first applying application circuitry power supply (AV.sub.dd =5v) to the application circuitry, and then applying a binary digital data signal (D0/D1) through the source-drain path of an access transistor (N3) in its on condition to the SRAM that controls the on/off condition of its associated controlled pass transistor (N4). This SRAM is typically one of a row-column array of similar SRAMs, and the access transistors for all SRAMs on the same row are similarly supplied with data signals through access transistors. The source-drain path of each pass transistor is connected between a separate pair of application circuitry interconnection points (A1, A2), whereby the on/off condition of this pass transistor determines whether or not these two points are going to be connected after the programming (or reprogramming) is terminated. While the data signal (D0/D1) is thus being applied to the SRAM, and while the power supply (PV.sub.DD) for the SRAM is being maintained at an intermediate level (3v) below the level of the application circuitry power supply voltage (AV.sub.dd =5v) and below the high binary level (D1), a row-select pulse (S) is applied to a control terminal of the access transistor, as well as to all control terminals of access transistors for accessing all other SRAMs on the same row as the SRAM under discussion. The row-select pulse (S) is then terminated and the SRAMs on other rows (if need be) are similarly written (or rewritten). Then the power supply (PV.sub.DD) for the SRAMs is increased to a level (PV.sub.DD =6v) advantageously higher, by a threshold of the pass transistor (N4), than that of the application circuitry (AV.sub.dd =5v), to reduce both voltage drops and power losses in pass transistors. In CMOS technology, in each SRAM the p-channel MOS transistor in both (cross-coupled) inverters have the same thresholds.

Multiple voltage supplies for field programmable gate arrays and the like

Disclosed is a method and an apparatus for range checking a value in a programmable system. An instruction prefix LDRNG enables the checking of a value against one or both limits of a range of values. The value is calculated as part of the execution of a primary instruction which is any suitable instruction, such as ADD, MOVE, STORE, etc., that directly follows the prefix. During the execution of the primary instruction the range check is performed, and an exception is taken without completing execution of the primary instruction if the value does not lie within the range.

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San Carlos, CA, United States of America

Dwight D Hill