Motorola Corporation

Dwight D Esgar

Ray D Sundstrom

Phuc C Pham

Mark B Weaver

Cleon Petty

Paul B Sofianos

Robert D Berger

An integrated circuit is divided into functional blocks. The integrated circuit includes current source based circuitry such as Emitter Coupled Logic (ECL), Current Mode Logic (CML), or Source Coupled Logic (SCL) Isolation blocks (14-20) are placed in signal paths to and from each functional block. A multiple output bias driver circuit (13) couples to each functional block. The multiple output bias driver circuit (13) provides a signal for enabling and disabling current sources of a functional block. A bias control logic circuit (12) controls the isolation blocks (14-20) and the multiple output bias driver (13). A functional block that is idle in the operation of the integrated circuit is shut down by the bias control logic circuit (12) to conserve power. The multiple output bias driver circuit (13) receives control signals from the bias control logic circuit (12) to turn off current sources in the idle functional block. Isolation blocks (14-20) receive control signals from the bias control logic circuit (12) to isolate the idle functional block and to provide a predetermined logic level in the signal paths from the idle functional to prevent propagation of an erroneous signal.

Circuit and method for isolating circuit blocks for reducing power

A non-saturating transistor circuit (11) having a first terminal (13), a control terminal (12), and a second terminal (14). The first terminal (13), control terminal (12), and second terminal (14) correspond respectively to a collector, base, and emitter of a transistor. The non-saturating transistor circuit (11) comprises a voltage divider (15), a diode (19), and a transistor (16). The voltage divider (15) enables the transistor (16) when a voltage is applied across the control terminal (12) and the second terminal (14) of non-saturating transistor circuit (11). The diode (19) removes current drive to the transistor (16) prior to the transistor (16) becoming saturated thus preventing the transistor (16) from saturating under all operating conditions.

Non-saturating bipolar transistor circuit

A gain stage for providing an automatic phase shift is provided. In particular, the gain stage detects whether an oscillation signal appears at its inputs. If an oscillation signal is not detected, then the gain stage inverts output signals occurring at outputs of a first amplifier before being respectively applied to inputs of a second amplifier. This has the overall effect of implementing a 180.degree. phase shift of a signal appearing at the outputs of the gain stage with respect to a signal appearing at the inputs of the gain stage.

Saw oscillator gain amplifier with auto phase shift

A split level differential bus having first and second signals at first and second lines, respectively, for transmitting data from a typical driver to a typical receiver, includes a first independent voltage source for terminating the first line and a second independent voltage source for terminating the second line, the second independent voltage source providing a voltage level that is different from the voltage level provided by the first independent voltage source. A current switch circuit controlled by the driver for switching current from the first line to the second line. A level shifting circuit coupled between the first line and the receiver for level shifting the first signal by a predetermined voltage.

Split level bus

A circuit having first and second inputs and first and second outputs includes a differential receiver circuit responsive to the first and second inputs for providing corresponding output logic signals at the first and second outputs. A tri-state detection circuit responsive to the first and second inputs and having an output for providing a first predetermined voltage to the differential receiver circuit when the first and second inputs are in a normal mode and for providing an increased second predetermined voltage to the differential receiver circuit when the first and second inputs are in a tri-state mode wherein oscillation of the differential receiver circuit is prevented and the outputs are forced to known logic states while the noise margin of the differential receiver is increased without a sacrifice in common mode range.

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Tempe, AZ, United States of America

Dwight D Esgar