Trw Limited

Northrop Grumman Systems Corporation

Dwight C Streit

Aaron K Oki

Donald K Umemoto

Liem T Tran

Augusto L Gutierrez-Aitken

Kevin Wesley Kobayashi

Thomas R Block

Frank M Yamada

George W McIver

Michael D Lammert

Michael Wojtowicz

Po-Hsin Liu

Edward M Garber

Daniel K Ko

Patrick T Chin

Eric N Kaneshiro

Chung-Hsu Chen

James R Velebir, Jr

Kin L Tan

Donald Katsu Umemto

Scott R Olson

Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector ( ) under the base ( ) along two parallel sides of the base mesa ( &mdash;FIG. ), and providing a sloped collector edge ( &mdash;FIG. ) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram ( &mdash;FIG. ) in which one pair of sides is in parallel with one of the said &lsqb; &rsqb; and &lsqb; {overscore (1)}&rsqb; planes of the crystalline structure and the other pair of sides in parallel with one of the &lsqb; &rsqb; and &lsqb; {overscore (1)} {overscore (1)}&rsqb; planes of the crystalline structure.

Ultra high speed heterojunction bipolar transistor having a cantilevered base

The invention relates to an integrated circuit structure that includes a substrate wafer having an active device layer disposed on a surface of the substrate wafer and having an electrically conductive element contained therein. The integrated circuit structure further comprises a barrier disposed between the substrate wafer and the active device layer, where the barrier blocks carriers injected into the substrate wafer and reduces low frequency oscillation effect.

Integrated circuit structure having a charge injection barrier

A method of selective molecular beam epitaxy for fabricating monolithically integrated circuit devices on a common substrate including combinations of PIN diode devices, HBT devices, HEMT devices and MESFET devices. The method includes depositing a profile layer of one of the devices on an appropriate substrate and then depositing a first dielectric layer over the profile layer. The profile layer and the dielectric layer are then etched to define a first device profile. A second profile layer for defining a second device is then deposited over the exposed substrate. The second profile is then selectively etched to define a second device profile. This process can be extended to more than two different device types monolithically integrated on a common substrate as long as the first developed devices are robust enough to handle the temperature cycling involved with developing the subsequent devices.

Method of fabricating monolithic multifunction integrated circuit devices

An acoustic charge transport device is formed by a process which introduces a process dependent variation in charge carrier density within the device. The acoustic charge transport device includes a transport channel operable to carry charge carriers in response to a surface acoustic wave. In addition, the acoustic charge transport device further includes a backgate for controlling the charge carrier density within the transport channel.

Backgate heterojunction acoustic charge transport device

The performance of a heterojunction bipolar transistor (HBT) operating at high power is limited by the power that can be dissipated by the device. This, in turn, is limited by the thermal resistance of the device to heat dissipation. In a typical HBT, and especially InP-based HBTs, heat generated during operation is concentrated near the collector-base junction. In order to more efficiently dissipate heat downward through the device to the substrate, both the collector and the sub-collector are formed of InP, which has a substantially lower thermal resistance than other typically used semiconductor materials.

Heterojunction bipolar transistor with reduced thermal resistance

A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.

High-frequency GaAs substrate based schottky barrier diodes

Method of fabricating high-frequency GaAs substrate-based Schottky

A heterojunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

Double photoresist layer self-aligned heterojuction bipolar transistor

A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (.beta.) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.

Method of fabricating very high gain heterojunction bipolar transistors

4-terminal HEMT-HBT composite devices, based upon monolithically integrated HEMT-HBT technology and configured in various topologies, are useful in a wide range of applications which currently utilize discrete MMICs. In particular, the 4-terminal topologies are easily configured as 3-terminal composite devices useful in various 2-port and 3-port MMIC circuit applications, such as low noise-high linearity amplifiers as well as mixers, which provide the benefits of a reduction in size, as well as corresponding cost while providing better performance than utilizing either HEMT or HBT devices individually.

Low noise-high linearity HEMT-HBT composite

A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

Method of fabricating double photoresist layer self-aligned

A method for fabricating an HBT in which the subcollector-base junction, which contributes to the base-collector capacitance of the device, is reduced by using a selective subcollector. In particular, subcollector areas of the device that do not contribute to collector resistance reduction are eliminated, thereby reducing the subcollector area, which, in turn, reduces the base-collector capacitance. As such, the maximum power-gain frequency f.sub.max is increased.

Method for making selective subcollector heterojunction bipolar

A pseudomorphic HEMT having a partially relaxed InGaAs channel layer. In order to increase device performance and lower the electron transport energy levels within the potential well defined by the conduction band of the channel layer, the channel layer thickness is increased beyond a critical thickness that defines where a strained InGaAs channel becomes relaxed and forms crystal lattice dislocations. The channel layer is partially relaxed in that the channel layer thickness exceeds the critical thickness, but the thickness of the channel layer is limited so that dislocations only form in a single direction.

Relaxed channel high electron mobility transistor

This invention discloses a heterojunction bipolar transistor (HBT) which includes a relatively thin intrinsic collector region and a relatively thick extrinsic collector region such that collector-base capacitance is reduced and electron transit time is maintained. The fabrication of the HBT includes loading a semi-insulating substrate into an molecular beam epitaxy machine, and growing a sub-collector contact layer, a bottom collector layer and a top collector layer on the substrate. Next, the substrate is removed from the molecular beam epitaxy machine and the top collector layer is etched by a photolithographic process to produce separate intrinsic and extrinsic collector regions. Then, the substrate is again loaded into the molecular beam epitaxy machine so that the base and emitter layers can be grown. And finally, the emitter layer is etched to form an emitter mesa only over the intrinsic semiconductor region.

Double-epitaxy heterojunction bipolar transistors for high speed

An InAlAs/InGaAlAs heterojunction bipolar transistor that includes a constant quaternary InGaAlAs collector layer. Graded InGaAlAs collector layers are provided on each side of the quaternary collector layer to minimize transitions through the constant collector layer. The InAlAs/InGaAlAs HBT may also include one or more of a graded InGaAlAs emitter-base transition region, a graded-doping InGaAs base layer, and a graded-composition InGaAlAs base layer.

Growing community of inventors

Seal Beach, CA, United States of America

Dwight C Streit