Hewlett-Packard Company

Ati Technologies Inc.

Mcdata Corporation

Dwayne R Bennett

Sanford S Lum

Clifford S Yeung

Wayne Wu

Keping Chen

Michael A Alford

Samuel L Wong

Samuel L C Wong

Samuel Lc Wong

The present invention relates to a video display processor comprised apparatus for receiving digital input signal components of a signal to be displayed, apparatus for converting the components to a desired format, apparatus for scaling and blending the signals in the desired format, apparatus for outputting the scaled and blended signals for display or further processing, and an arbiter and local timing apparatus for controlling the apparatus substantially independently of a host CPU.

Host CPU independent video processing unit

A method and apparatus for delaying frames received asynchronously from a fiber channel port until receive memory is properly sequenced for storing the delayed frames in which a circular buffer is positioned on the data path between the fiber channel port and the receive memory for delaying the frames in accordance with control signals generated by a sequencer having knowledge of the receive memory sequence count.

Method and apparatus for memory sequencing

A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. A channel module, which is disposed between a switch module and a plurality of fiber optic channels, comprises a port intelligence system and a memory interface system. The port intelligence system is responsible for transmitting and receiving data from the fiber optic channels in accordance with a predetermined protocol, preferably Fibre Channel. The memory interface system comprises a receive memory unit, a transmit memory unit and memory control logic. When an intermix frame is to be passed through the switch, the intermix frame is passed to the buffer concurrently while class 1 data transfer occurs via the bypass bus. After the intermix frame has been completely written into the buffer, the memory control logic waits to detect a tag indicative of a break in the class 1 data transfer. The control logic will then switch the MUX and cause the buffer to commence writing the intermix frame to the port intelligence system for transfer to a predetermined fiber optic channel.

Bypass switching and messaging mechanism for providing intermix data

The present invention relates to an image scaler comprised of apparatus for receiving coefficients a and b and image display values of adjacent pixels P and Q respective of an image, apparatus for repeatedly operating on the coefficients and values for successive pixels according to the transform ##EQU1## where SUM is the sum of the coefficients,

Method and apparatus for scaling and blending an image to be displayed

The invention is a method and apparatus for transmitting frames from a plurality of node ports (N.sub.-- ports) to their associated fabric ports (F.sub.-- ports) for forwarding to other interconnected F.sub.-- ports on a Fibre Channel switch in which the transmitted frames are stored in a plurality of receive buffers at the associated F.sub.-- port prior to forwarding to an interconnected F.sub.-- port, and a receive credit counter, a smart credit counter and a transmit credit counter are employed for tracking the availability of the receive buffers.

Method and apparatus for tracking buffer availability

A channel module has an interchangeable port intelligence system at a front end which is connected to a memory interface system at a back end. Each port intelligence system provides one or more ports for connection to fiber optic channels and, the various port intelligence systems are distinguishable by a particular bit rate in which each supports. Data from the port intelligence system is bit sliced and forwarded to the memory interface system. In the system, the data is stored in receive memory in a distributed manner over a plurality of receive memory components. The bit slicing simplifies the input/output interface to the receive memory and enables storage of data with a common format, regardless of the rate at which the data was received from the channel. When data is read from the receive memory, each of the receive memory components contributes bits in order to reconstruct the data.

Channel module for a fiber optic switch with bit sliced memory

A method and apparatus for high speed decoding of a 20 bit wide data into 16-bit wide data in which the first ten bits and the lower ten bits are decoded simultaneously to ensure complete decoding and where the decoding of the second ten bits is dependent upon the running disparity of the first ten bits, the second ten bits are decoded twice, one assuming the decoded first ten bits will have a positive running disparity, and a second time assuming that the decoded first ten bits will have a negative running disparity.

Method and apparatus for transmission code decoding and encoding

A system and method for inserting intermix frames into a continuous stream of class 1 frames. A bypass bus, in conjunction with a first-in-first-out (FIFO) buffer, are provided within a fiber optic switch element, to route intermix data frame through the switch that is concurrently transmitting class 1 data. A channel module, which is disposed between a switch module and a plurality of fiber optic channels, comprises a port intelligence system and a memory interface system. The port intelligence system is responsible for transmitting and receiving data from the fiber optic channels in accordance with a predetermined protocol, preferably Fibre Channel. The memory interface system comprises a receive memory unit, a transmit memory unit and memory control logic. When an intermix frame is to be passed through the switch, the intermix frame is passed to a FIFO concurrently while class 1 data transfer occurs via the bypass bus. After the intermix frame has been completely written into the FIFO, the memory control logic waits to detect a tag indicative of a break in the class 1 data transfer. The control logic will then switch the MUX and cause the FIFO to commence writing the intermix frame to the port intelligence system for transfer to a predetermined fiber optic channel.

Growing community of inventors

Scarborough, Canada

Dwayne R Bennett