Freescale Semiconductor,inc.

Nxp B.v.

Nxp Usa, Inc.

Dwarka Prasad

Zameer Iqbal

Amar Kumar Yadav

Douglas Michael Reber

Ertugrul Demircan

Glenn Charles Abeln

Jwalant Kumar Mishra

Jainendra Singh

Rajat Kohli

Prokash Ghosh

Donald E Smeltzer

Kenneth J Danti

Jyotirmoy Ghosh

Indu Bala

Inder Mohan Bhawnani

A memory power control unit, MPCU, is provided for preventing unauthorised access to data stored in a volatile memory, the MPCU comprising a power controller comprising an input configured to receive a signal from a tamper detection circuit, a first supply input configured 5 to receive a first supply voltage, a first reference input configured to receive a first reference voltage, a supply output configured to output a supply voltage to the volatile memory, a reference output configured to output a reference voltage to the volatile memory, wherein, in response to receipt of a signal at the input indicative of an attempt to tamper with the volatile memory, the power controller is configured to output a reduced supply voltage via the supply 10 output for a first predetermined time period, wherein the reduced supply voltage is less than the first supply voltage.

Memory power control unit

A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.

Method for verifying design rule checks

An electronic design automation (EDA) tool generates first and second instances, which are different in at least one aspect, of a cell representing a device, allowing a user to initiate an abutment of the first and second instances in a layout canvas, reads a position and orientation of each of the first and second instances to be abutted from the layout canvas, evaluates the respective positions and orientations of the first and second instances, altering a component of one of the first and second instances based on the evaluation, and then automatically abuts the first and second instances following the alteration of the component of the one of the first and second instances.

Method and apparatus for abutting p-cell layout based on position and orientation

An electronic design automation (EDA) tool for adding a feature to a target parameterized cell (pcell) in an electronic circuit design includes a memory that stores the electronic circuit design, and a processor in communication with the memory. The processor defines a specification of an add-on pcell. The specification includes a feature to be added to the target pcell. The processor reads the properties associated with the target pcell and generates the add-on pcell based on its specification and the properties of the target pcell. The add-on pcell then is instantiated and bound to the target pcell, which adds the feature to the target pcell.

Method of adding features to parameterized cells

Growing community of inventors

Noida, India

Dwarka Prasad