Emulex Corporation

Cirrus Logic Inc.

Aspeed Technology Inc.

Dwarka Partani

Sujith Arramreddy

Melanie Fike

Vlad Bril

Balakrishna Jayadev

Rakesh Kumar Bindlish

Sagar Waman Kenkare

Wilfred A Smith

In one embodiment, a monolithic integrated circuit includes a first UART, a second UART, and a multiplexer. The first UART has a parallel IO interface to couple to a host system to transceive parallel data and a serial IO interface. The second UART has a parallel IO interface and a serial IO interface coupled to the serial IO interface of the first UART. The first and second UARTs convert parallel data into serial data and serial data into parallel data. The multiplexer has an output coupled to the serial input of the first UART, a first input coupled to the serial output of the second UART, a second input coupled to a serial input of a serial communication port, and a select input coupled to a control signal selectively coupling serial interfaces of first and second UARTs together for remote terminal services at a remote computer system over a network.

Systems with virtual universal asynchronous receiver transmitter and methods therefor

A feedback subsystem may be used to control the positioning of a local cursor of a display in response to receiving remote cursor movement information from a remote computer system. The feedback subsystem may send the remote cursor movement information to an operating system (OS) which may send local coordinate information to a graphics controller. Local coordinate information from the graphics controller may be used to compare with remote coordinate information received from the remote computer system. The feedback subsystem may repeatedly send the remote cursor movement information to the OS until it is determined that the local coordinate information from the graphics controller is consistent with the remote coordinate information received from the remote computer system.

Hardware cursor snooping

Virtual universal asynchronous receiver transmitter for server systems

In one embodiment of the invention, a server system is disclosed for data processing having a printed circuit board with one or more processors to process data; a network interface controller coupled to the one or more processors; and a monolithic integrated circuit (IC) coupled to the one or more processors and the network interface controller. The network interface controller couples the server system to a network for remote client access to the server system. The monolithic integrated circuit couples a remote computer system to the server system via the network. The remote computer system includes a remote storage device, a remote display, a remote keyboard, and a remote mouse to allow remote control and management of the server system.

Methods, apparatus, and systems for integrated management, graphics and I/O control of server systems

Modification to frame buffer memory information associated with a first display may be used to update information displayed on a second display. The first display may be mapped to a matrix of display areas. The modification to the frame buffer memory information may be detected be detecting write memory address. One or more display areas affected by the modification to the frame buffer memory information may be identified based on display parameters associated with the first display. Frame buffer memory information associated with the one or more affected display areas may be retrieved and compressed before being transmitted over a communication link to be displayed on the second display.

Methods and apparatus for non-intrusive capturing of frame buffer memory information for remote display

The display controller of the present invention reduces power consumption by suppressing clock signals to a display memory (comprising SGRAM or SDRAM) between screen refreshes and memory accesses. The present invention takes advantage of power-down modes provided for SGRAM and/or SDRAM memories which are used in the prior art to place a memory in an active suspend mode. Further energy savings are realized and memory bandwidth increased when using a display memory comprising two banks. When one bank of memory is being accessed, the other bank of memory is precharged and activated. Succeeding pages of memory are placed in alternate banks of display memory. Thus, then data is to be accessed from a next page of memory, the corresponding bank is already charged and ready to be accessed.

Method and apparatus for optimizing power consumption and memory

A VGA compatible graphics controller receives character data, attribute data and font data, each of which are stored in different planes of a display memory. The font data comprises bit maps of at least two character fonts, which may be user fonts or default fonts loaded from a controller BIOS. The video controller detects attempts by a host CPU to write data into plane two of display memory (where character font bit maps reside). The address generated by the host CPU is scrambled to produce a video font cache address. The character font bit maps are stored in a video font cache at the scrambled address. The font select bits of the CPU generated address are used as a byte select to store a particular font at a byte location at a selected video font cache address. In the preferred embodiment, eight fonts may be stored in the video font cache, one scan line each font of each character as a different byte at each address of the video font cache in a 64 bit wide DRAM.

Growing community of inventors

San Jose, CA, United States of America

Dwarka Partani