International Business Machines Corporation

Fujitsu Corporation

Duy Q Huynh

Flavio Alvarenga Bergamaschi

Santhosh Rao

Kenneth Michael Ashcraft

Loc Tien Tran

Erin Christine Burke

Duc J Vianney

Viktors Bertsis

Robert G Baker

Suksoon Yong

Peter Wai Yee Wong

Paul R Swingle

Prabhakara Rao Vadapalli

Yannis Labrou

Dennis L Moeller

Zhexuan Song

Giang Chau Nguyen

Jose A Eduartez

Ryusuke Masuouka

Gahn Wattanadilok Krishnakalin

Lyndsi R McKinney

Peter Wai Yu Wong

Kim V Lam

Raymond Roger Trombly

A method, a system and a computer program product including instructions for verification of the integrity of a shared memory using in line coding is provided. It involves an active step wherein multiple bus masters write a corresponding data to a shared memory. After that it also includes a verification step where data entered in the shared memory by multiple bus masters is verified.

Verifying shared memory integrity

A method and system to minimize redundancy in testing a new software system by utilizing a knowledge base is provided. The knowledge base may be represented in a form of a decision tree including leaf nodes which store previously tested optimal configurations. When the knowledge base does not contain an optimal configuration for the new software, an optimal solution for the new software system may be determined by adding a further decision tree branch to the initial decision tree. A desirable tree branch may be selected from a table including a predetermined set of desirable tree branches for each category of software. As a result, the number of solutions to be tested on the input software may be limited and cost and effort to run redundant tests on a software system may be reduced.

Method and system for optimizing configuration classification of software

A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply a second test vector at a second time before the duration but substantially after the first time. The simulator can collect a response from the multiple core integrated circuit based on the first test vector and the second test vector.

Method and apparatus for scheduling test vectors in a multiple core integrated circuit

A method and system to minimize to redundancy in testing a new software system by utilizing a knowledge base is provided. The knowledge base may be represented in a form of a decision tree including leaf nodes which store previously tested optimal configurations. When the knowledge base does not contain an optimal configuration for the new software, an optimal solution for the new software system may be determined by adding a further decision tree branch to the initial decision tree. A desirable tree branch may be selected from a table including a predetermined set of desirable tree branches for each category of software. As a result, the number of solutions to be tested on the input software may be limited and cost and effort to run redundant tests on a software system may be reduced.

Task Computing computer system by segmenting the system into a plurality of implementation tiers of a presentation layer, a remote procedure call programming interface (API), a middleware layer to which the presentation layer interfaces via the remote procedure call API to real-time, dynamically generate a computer implemented task interface at the presentation layer to a semantically described source of function as a service on a computer system, and a service layer and a function source realization layer providing the semantically described source of function as the service on the computer system to which the middleware layer interfaces. Real-time and dynamically composing an executable task that comprises one or more services using the generated task interface at the presentation layer to one or more services on the computer based upon the semantically described application-, device- and service-rich computer.

Task computing

A homograph filter and method which increase the probability that homographs are pronounced correctly in a speech synthesis system utilizes a filter engine operating in conjunction with a set of rules. The filter engine parses a textual sentence to extract any present homographs and applies a correct set of rules to the homograph, based on an optimal search algorithm. The engine then carries out any appropriate substitution of phonetic data. Rules are primarily based on syntactic analisis, based on a priori knowledge of how each homograph is used. The rule set is classified into different categories in order to optimize the search algorithm and to allow the rules to be modified and updated incrementally without effecting the engine construction and/or performance. The search algorithm utilizes syntactic analysis to achieve optimum results. If syntactic analysis does not yield a satisfactory result, semantic analysis could also be utilized to determine the usage of the homograph based on the contents of the items which surround the homograph. The rule set contains a set of grammatical rules to perform syntactic analysis. If syntactic or semantic analysis does not yield a result, the result will be based on the statistical usage of the given homograph.

Homograph filter for speech synthesis system

A computer system having a peripheral bus and a digital signal processor (DSP) local bus interfacing to the peripheral bus via an extended bus interface circuit (EBIC). The DSP local bus is configured such that devices, which are typically two or more DSPs, electrically connected to the DSP local bus may transfer data to other devices connected to the DSP local bus regardless of data transfer activity of the peripheral bus. Moreover, as seen from the peripheral bus, the devices connected to the DSP local bus have the same arbitration level. However, as seen from the DSP local bus, each device connected to the DSP local bus has a unique arbitration level determined by the priority of the tasks executing on the respective devices, as determined by a DSP operating system.

Computer system having a DSP local bus

This invention relates to personal computers, and to the handling of input/output signals exchanged between a microprocessor included within a personal computer and devices remote from the microprocessor. In addition to the microprocessor and a system board mounting the microprocessor, a personal computer in accordance with this invention has an input/output signal processing circuit for performing logical operations on digital signals passing to and from the microprocessor and preparing such signals for operative communication between the microprocessor and devices remote from the microprocessor, a second circuit board for mounting the circuit, a board connector mounting the second circuit board on the system board, an input/output connector for passing signals to and from the circuit for receipt from and delivery to devices remote from the microprocessor, and a signal communicating member extending between the circuit and the input/output connector for operatively communicating signals therebetween.

Personal computer with input/output subsystem

This invention relates to personal computers having the capability for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate system controller; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus. Provision is made for setting a status bit to identify to software such as diagnostic software which microprocessor is functioning as the system controlling processor.

Personal computer with alternate system controller and register for

A DSP manager acquires through software techniques configuration and related data for multimedia hardware devices from BIOS device drivers interposed to functionally insulate the resource manager from hardware device specific information. The DSP manager manages tasks executing on hardware devices in a multiple DSP environment. The DSP manager optimally assigns tasks, loads tasks, and removes tasks for a function without interrupting execution of tasks making up other functions.

System and method for efficiently loading and removing selected

A personal computer housing has a plurality of air intake openings located around the sides and front. A fan is mounted at the rear of the housing and sucks or draws coolant air through the intakes and exhausts the air to the rear. A bulk power supply is mounted along one side of the housing and is cooled by air flow through adjacent intakes. A plurality of I/O or expansion cards are located along the opposite side of the housing and cooled by air flowing through adjacent side intakes. A plurality of system cards including a processor card and memory cards, are located in parallel, rearwardly extending rows directly between at least some of the front intakes and the fan. A DC/DC regulator card is mounted over the system cards and has a heat sink provided with rearwardly extended cooling fins aligned in the direction of air flow from front to rear.

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Boca Raton, FL, United States of America

Duy Q Huynh