Texas Instruments Corporation

Duy-Loan T Le

Scott E Smith

Kenneth A Poteet

Roger D Norwood

Karl M Guttag

Wilbur Christian Vogley

Steven D Krueger

Anthony M Balistreri

Joseph H Neal

Joseph P Hartigan

Michael C Stephens, Jr

Michael Duc Ho

Sanjive Agarwala

Bryan David Sheffield

Mark Allen Gerber

Ernest J Russell

Daniel A Baudouin

Joel J Graber

David N Walter

James S Wallace

Manjeri Krishnan

Charles J Pilch

Masayoshi Nomura

Kallol Mazumder

Yutaka Komai

Anh Bui

M Kumar Rajith

Arthur R Piejko

Terry T Tsai

Michael V Ho

Duc Ho

Carl W Perrin

A device has a first semiconductor chip () with contact pads in an interior first set () and a peripheral second set (). A deformed sphere () of non-reflow metal such as gold is placed on each contact pad of the first and second sets. At least one additional deformed sphere () is placed on the first set pads, forming column-shaped spacers. The first chip is attached to a substrate () with a chip attachment location and a third set of contact pads () near the location. Low profile bond wires () span between the pads of the third set and the second set. A second semiconductor chip () of a size has a fourth set of contact pads () at locations matching the first set pads. The second chip is placed over the first chip so that the fourth set pads are aligned with the spacers on the matching first set pads, and at least one edge of the second chip overhangs the sphere on at least one pad of the second set. A reflow metal () bonds the spacers to the second chip, while the spacers space the first and second chips by a gap () wide enough for placing the wire spans to the second set pads.

Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices

Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.

Electrical fuse control of memory slowdown

A circuit (,) that drives word lines and tests a word line (,) in a semiconductor device is disclosed. A charge circuit (,) couples a supply voltage (VPP) to a charge node (,) according to a potential at a boot node (,). The charge node (,) supplies a charge voltage for the word line (,). In a standard cycle, the boot node (,) is charged to a high voltage, and maintained at the high potential, to keep the word line (,) charged. In a test cycle, the boot node (,) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (,) and the word line (,). In the event the word line (,) suffers from current leakage, a drop in potential will be detected at the charge rode (,).

Circuit for driving conductive line and testing conductive line for current leakage

A circuit is designed with a detector circuit (,) coupled between a supply voltage terminal (,) and a reference voltage terminal (,). The detector circuit produces a first control signal in response to a detected mode and produces a second control signal in response to another mode. A first circuit (,) including a delay circuit receives the first control signal and a third control signal. The delay circuit produces a fourth control signal at an output terminal (,) in response to the first and third control signals. A second circuit (,) receives the second control signal and the third control signal. The second circuit produces the fourth control signal at the output terminal in response to the second and third control signals.

Timing circuit for high voltage testing

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

High-speed memory arranged for operating synchronously with a

A read mask circuit (300) is disclosed. A mask command is shifted through a series of mask latches (308 and 310) to generate the output-enable input (OE.sub.--) of an output driver (306). In synchronism with the mask command, data bits are shifted through a series of data latches (312 and 314) to the data input (DIN) of the output driver (306). To prevent a race condition between the mask command and the data bit that is to be masked (B3), the mask command, when latched in the second-to-last mask latch (308), is used to interrupt the last data latch (314). This prevents the to-be-masked data bit (B3) from being latched in the last data latch (314) and generating an undesirable output data transition by the output driver (306).

Data pipeline interrupt scheme for preventing data disturbances

High speed memory arranged for operating synchronously with a

Data processing system arranged for operating synchronously with a high

An integrated circuit memory device (10) includes a large on-chip capacitor (12) that has a high voltage plate and a low voltage plate. The large on-chip capacitor (12) stores charge for a positive voltage supply (VPP) for the integrated circuit memory device (10). The high voltage plate of the large on-chip capacitor (12) is connected to a node (NODE 1) for distributing charge from the large on-chip capacitor. A load (16) is connected to the node (NODE 1) and consumes charge from the high voltage plate to power operations of the integrated circuit memory device (10). The load (16) includes a memory array comprising a plurality of memory cells. The low voltage plate of the large on-chip capacitor (12) is connected to a capacitive voltage reference which has high capacitance and has a voltage-level greater than ground potential and less than the positive voltage supply. In one embodiment, the large on-chip capacitor is a storage/filter capacitor (12) for a boosted high voltage supply (VPP), and the capacitive voltage reference is a memory cell reference voltage (VPLT) which is also connected to a reference plate of memory cell capacitors (28) of the memory cells (20) in the memory array.

Integrated circuit memory device having reduced stress across large

Random access memory with latency arranged for operating synchronously

A semiconductor memory device 40 includes an array of storage cells 130, addressable by row and column and specifically designed for testing. Row and column addresses are decoded to access a row and plural columns simultaneously. A test data bit to be written into the storage cells is replicated and stored into as many storage cells at once as there are columns simultaneously accessed. Upon readout for a comparison test, plural occurrences of the stored test data bit are compared with each other and with an expected data bit within parallel comparator circuitry 140 located within the memory device. A pass/fail signal (on lead 170) from the parallel comparator circuitry is transmitted to the memory device tester 30 for final defect analysis and correction. When a failure/defect is detected, information representing the address and the type of failure are stored in the memory device tester. A memory device test method also is described.

Testing and repair of wide I/O semiconductor memory devices designed for

The invention discloses a high density semiconductor package. Two semiconductor chips are each affixed on a corresponding one of two lead frames. The semiconductor chips and the lead frames are encapsulated, wherein only a portion of the leads of the lead frames protrudes and extends from the package.

High density semiconductor package

Random access memory arranged for operating synchronously with a

Growing community of inventors

Missouri City, TX, United States of America

Duy-Loan T Le