International Business Machines Corporation

Dustin James VanStee

Kevin Charles Gower

Thomas J Griffin

Kirk David Lamb

Carl E Love

Elianne A Bravo

Warren Edward Maule

Kyu-hyoun Kim

David D Cadigan

M Dean Sciacca

Steven J Hnatko

Kenneth Y Chan

Leonard M Greenberg

Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.

Performance evaluation of solid state memory device

Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition.

Solid state memory device logical and physical partitioning

A computer system having a host adapter is provided. The host adapter includes a primary port that follows a primary communication protocol. The primary port is connectable to at least one peripheral device. The host adapter includes a service port that follows a service communication protocol to monitor and send recovery commands to the peripheral device. The service port is decoupled and separate from the primary port and connectable to the at least one peripheral device.

Service channel for connecting a host computer to peripheral devices

A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.

Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device

A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.

System and method for providing voltage power gating

Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.

Systems for providing performance monitoring in a memory system

A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred. The logic further facilitates processing the commands if the commands are directed to the MID and redriving the commands via the second connection onto the high speed bus.

System and method for providing a configurable command sequence for a memory interface device

Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.

Systems and methods for providing collision detection in a memory system

A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting.

System and method for providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system

Systems and methods for providing a dynamic memory buffer bank policy. Embodiments include a hub device for selecting a bank page policy. The hub device includes an input command stream interface and a bank page policy module. The input command stream interface detects commands from a memory controller that are directed to one or more memory devices that are connected to the hub device. The bank page policy module independently analyzes the commands to determine access patterns to the memory devices and for dynamically selecting between an open bank page policy and a closed bank page policy for the memory devices based on the analysis.

Systems and methods for providing a dynamic memory bank page policy

Systems and methods for providing dynamic memory pre-fetch. Embodiments include a hub device including an input command stream interface and an adaptive pre-fetch logical unit (APLU). The input command stream interface detects commands from a memory controller directed to one or more memory devices that are connected to the hub device. The APLU independently analyzes the commands to determine access patterns to the memory devices. The APLU also dynamically selects between enabling a pre-fetch function and disabling the pre-fetch function for the memory devices based on the results of the analysis.

Systems and methods for providing dynamic memory pre-fetch

Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.

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Poughkeepsie, NY, United States of America

Dustin James VanStee