Apple Inc.

Keysight Technologies, Inc.

Dusan Stepanovic

Mansour Keramat

Ali Mesgarani

Hyunsik Park

Farzan Farbiz

Seyedeh Sedigheh Hashemi

Ashirwad Bahukhandi

Vahid Majidzadeh Bafar

Ke Yun

KiYoung Nam

Sedigheh Hashemi

Ahmad Al Marashli

Mahdi Khoshgard

Sudharsan Kanagaraj

Hamid Nejati

Albert Hsu Ting Chang

The present disclosure describes a system with an antenna, a signal generator, data converters, and an aggregator circuit. The antenna is configured to provide an input signal to the data converters. The signal generator is configured to generate a random binary sequence received by the data converters. The data converters include an analog circuit and a digital circuit configured to sample positive and negative polarities of the input signal based on the random binary sequence, reducing an offset tone in an output spectrum produced by the aggregator circuit.

Data converter with offset tone reduction

A sensor system included in an integrated circuit includes multiple sensor circuits and a control circuit. Using characterization data, a model may be generated that defines a relationship between measurable parameters of the integrated circuit and an operating characteristic of the integrated circuit. The control circuit can combine, using a function included in the model, data from the multiple sensor circuits to determine a value of the operating characteristic that is more accurate than a sensor circuit configured to measure a single parameter of the integrated circuit that varies with the operating characteristic.

Process-insensitive sensor circuit

Systems, apparatuses, and methods for performing digital pre-distortion compensation of digital-to-analog converter non-linearity are described. A correction circuit receives a digital input word and couples a portion of the most significant bits (MSB's) of the digital input word to a correction lookup table (LUT). A correction value is retrieved from a correction LUT entry that matches the MSB's of the digital input word. Next, the correction value is added to the original digital input word in the digital domain. Then, the sum generated by adding the correction value to the original digital input word is optionally clipped if the sum exceeds the DAC core's input range. Next, the DAC core converts the sum into an analog value that is representative of the digital input word. The above approach helps to reduce non-linearities introduced by the DAC core in an energy-efficient manner by performing a correction in the digital domain.

Digital pre-distortion compensation of digital-to-analog converter non-linearity

Systems, apparatuses, and methods for performing hybrid non-linearity correction for a digital-to-analog converter (DAC) are described. A circuit includes two correction LUTs, an edge-trim DAC, and a DAC core. A lookup of a first correction LUT is performed using a portion of the most significant bits (MSBs) of a received digital input value. A first correction value, retrieved from the first correction LUT, is applied to the digital input value to generate a corrected value. The corrected value is provided to the DAC core and to a second correction LUT. A second correction value, retrieved from the second correction LUT, is compared to the first correction value. If the second correction value is different from the first correction value, the difference is provided to the edge-trim DAC to generate an analog correction which is applied to an analog output of the DAC core.

Hybrid digital-to-analog converter non-linearity calibration

An image sensing system and methods for operating the same are disclosed. An image sensing system includes a plurality of pixel circuits, a multiplexer configured to select one of the pixel circuit and provide analog pixel data without sampling, and a successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert the analog pixel data into digital data. The SAR ADC includes a capacitive digital-to-analog converter (CDAC) configured to convert contents of the SAR into a corresponding analog signal for comparison, by a comparator, with the analog pixel data. The CDAC includes a two-dimensional array of circuit elements. A control circuit in the image sensing system is configured to cause random ones of the circuit elements of the CDAC to be selected for generation of the corresponding analog signal and add a dithering signal so a CDAC output and shuffle a multiplexer switch sequence to improve fixed pattern noise.

Low noise image sensor system with reduced fixed pattern noise

An image sensing system is disclosed. The image sensing system includes an array of pixel circuits and a multiplexer configured to convey an output signal from a selected one of the pixel circuits. The output signal from the selected one of the plurality of pixel circuits is converted from analog to digital by a successive approximation register (SAR) analog-to-digital converter (ADC). A control circuit is provided to cause the SAR ADC power cycling with shaped power control signal. The SAR ADC comparator pre-amp with integrate-reset causes reduced power to the theoretical limit for imaging systems. The control circuit causes quantization process of selected ones of the pixel circuits to be repeated one or more times during the processing.

High speed, low power image sensor system

In various embodiments, at least one analog-to-digital converter (ADC) channel circuit may be used to convert an analog input signal into an output digital signal. A comparator threshold adjustment circuit may pseudorandomly modify at least one comparator threshold. A postprocessing circuit may identify, based on outputs of the ADC channel circuits, an ADC coefficient and may modify an output digital signal based on the ADC coefficient. As a result, the ADC channel circuits may more accurately convert the analog input signal into an output digital signal, as compared to a system that uses ADC channel circuits but does not include a postprocessing circuit. Further, a similar result may be obtained, as compared to a system that uses a higher gain amplifier, a higher speed amplifier, or both, but does not modify the one or more outputs.

Analog-to-digital converter circuit calibration system

A charge redistribution SAR analog-to-digital converter includes a source of a reference voltage, a digital-to-analog converter, and a reset circuit. The digital-to-analog converter includes converter stages that range in significance from most significant to least significant. Each converter stage includes respective capacitors and switches. The switches are controllable to selectively connect the capacitors to the reference voltage or to ground. The capacitors of the converter stages are weighted in capacitance in accordance with significance of the converter stage. The reset circuit is to control the switches to reset the converter stages with a temporal offset between at least two of the converter stages. The temporal offset between the at least two of the converter stages reduces the dependence of the charge drawn from the reference voltage source during each conversion cycle on the sample of an analog input signal converted to a digital value during the conversion cycle.

Charge-redistribution SAR ADC with sample-independent reference current

A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.

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Mountain View, CA, United States of America

Dusan Stepanovic