Nxp B.v.

Imec

Katholieke Universiteit Leuven

Dusan Golubovic

Johannes Josephus Theodorus Marinus Donkers

Tony Vanhoucke

Rob Van Dalen

Hans Mertens

Gerhard Koops

Gilberto Curatola

Michiel Jos Van Duuren

Maarten Jacobus Swanenberg

Wim Magnus

Nader Akil

Guillaume Boccardi

Christoph Kerner

Almudena Huerta

Mohamed Boutchich

The invention relates to a multi-transistor, e.g. a two-transistor memory cell with an enhancement junction field effect transistor (JFET) as the access gate transistor. In one embodiment, the JFET is provided as a self-aligned JFET. Accordingly, and advantageous over the prior art, the invention allows for a method for manufacturing a multi-transistor, e.g. a two-transistor memory cell comprising a JFET as the access transistor without adding any additional masks and/or processing steps. Such a multi-transistor, e.g. a two-transistor memory cell according to invention, provides an improved reliability.

Multi-transistor memory cell with an enhancement junction field effect transistor (JFET) as the access gate transistor

A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.

Tunnel field effect transistor

Various exemplary embodiments relate to an isolation device including a semiconductor layer and an insulation layer. The insulation layer insulates a central portion of the semiconductor layer. A high voltage terminal connects to the insulation layer, a first low voltage terminal connects to a first non-insulated portion of the semiconductor layer, and a second low voltage terminal connects to a second non-insulated portion of the semiconductor layer. The first and second low voltage terminals are electrically connected via the semiconductor layer. A voltage applied to the high voltage terminal influences the conductance of the semiconductor layer. The high voltage terminal is galvanically isolated from the first and second low voltage terminals.

Galvanic isolation device and method

A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.

Nonvolatile memory cell comprising a nanowire and manufacturing method thereof

An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

Optocoupler circuit

A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the method comprises providing an electrical signal, e.g. a current, in an input ring magnetically coupled to a computational element, which generates a magnetic field in the computational element and sensing the change in the current and/or voltage of an output element magnetically coupled to the computational element. The electrical input signal can be an AC signal or a DC signal. The computational element is electromagnetically coupled with other adjacent computational elements and/or with the interface elements. The corresponding magnetic flux between the computational elements and/or the interface elements acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements.

Method of operating quantum-mechanical memory and computational devices

Growing community of inventors

Leuven, Belgium

Dusan Golubovic