Intel Corporation

Durgesh Borkar

Subramaniam M Maiyuran

Varghese George

Jorge E Parra

Chandra S Gurram

Ashutosh Garg

Shubra Marwaha

Supratim Pal

Darin Starkey

Dipankar Das

Naveen K Mellempudi

Yan Li

Chunhui Mei

Sasikanth Avancha

Wei Xiong

Yongsheng Liu

Dharma Teja Vooturi

Kiran Chand Veernapu

Arijit Mukhopadhyay

VijayKumar Donthireddy

An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.

Utilizing structured sparsity in systolic arrays

Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.

Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.

Embodiments provide for a graphics processing apparatus comprising a graphics processing unit having fixed point logic to convert YUV encoded image data to RGB encoded image data. In one embodiment the fixed point logic includes a set of fixed function logic circuits to compute a set of fixed point approximations of specified floating point color space conversion coefficients during the conversion of the YUV encoded image date to the RGB encoded image data.

Color space conversion logic having reduced conversion error

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Folsom, CA, United States of America

Durgesh Borkar