Intel Corporation

Durgaprasad Bilagi

Abhishek R Appu

Joydeep Ray

Altug Koker

Subramaniam M Maiyuran

Vasanth Ranganathan

Sanjeev S Jahagirdar

Scott R Janus

Xinmin Tian

Brent E Insko

Pattabhiraman K

Elmoustapha Ould-Ahmed-Vall

Varghese George

Nikos Kaburlasos

Lidong Xu

Aravindh V Anantaraman

James M Holland

Lakshminarayanan Striramassarma

Valentin Andrei

Sungye Kim

Guei-Yuan Lueh

Changliang Wang

Vidhya Krishnan

Aditya Navale

Ben J Ashbaugh

Naveen Matam

Chien-Wei Li

Described herein is a graphics processor comprising a processing resource configured to perform processing operations, a codec configured to compress and decompress data associated with the processing operations, and circuitry configured to calculate a metadata address for a compressed surface based on a flat virtual memory address mapping between the address of the compressed surface and the metadata address. The compressed surface is to store data associated with a processing operation to be performed by the processing resource and the metadata address is a virtual address that stores compression metadata for the compressed surface. The circuitry can configure the codec to access the compressed surface based on the compression metadata.

Compression using a flat mapping in virtual address space

Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

Graphics processing unit processing and caching improvements

One embodiment provides an apparatus comprising a graphics processor device including a first compute engine and a second compute engine, wherein the second compute engine includes a subset of the functionality provided by the first compute engine and a lower power consumption relative to the first compute engine.

Low power inference engine pipeline in a graphics processing unit

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

Systems and methods for cache optimization

Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Systems and methods for error detection and control for embedded memory and compute elements

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

Systems and methods for cache utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

Growing community of inventors

Folsom, CA, United States of America

Durgaprasad Bilagi