International Business Machines Corporation

Other

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Mentor Graphics Corporation

Kabushiki Kaisha Toshiba

Dureseti Chidambarrao

Omer H Dokumaci

Oleg Gluschenkov

Jack Allan Mandelman

William K Henson

Kern Rim

Brian Joseph Greene

Bruce Bennett Doris

Carl John Radens

Huajie Chen

Huilong Zhu

Shreesh Narasimha

Ramachandra Divakaruni

Haining S Yang

Judson Robert Holt

Richard Quimby Williams

Michael P Belyansky

Yue Liang

Xiaojun Yu

Jason D Hibbeler

James A Culp

Ying Li

Siddhartha Panda

Lawrence Alfred Clevenger

Chandrasekharan Kothandaraman

Xiao Hu Liu

Gregory Gower Freeman

Kaushik Arun Kumar

Deok-Kee Kim

Henry K Utomo

Louis L Hsu

Geng Wang

Xiangdong Chen

Dominic Joseph Schepis

Rajarao Jammy

Dongbing Shao

Werner A Rausch

Paul S Chang

Shayak Banerjee

Kangguo Cheng

Jeffrey W Sleight

Marwan H Khater

Renee Tong Mo

Meikei Ieong

Qiqing Christine Ouyang

Jochen C Beintner

Stephen Edward Greco

Sunfei Fang

Jun Yuan

David R Hanson

Devendra K Sadana

Edward J Nowak

William R Tonti

Toshiharu Furukawa

John J Ellis-Monaghan

Son Van Nguyen

Tsutomu Sato

James William Adkisson

Ramachandran Muralidhar

John Joseph Pekarik

Tymon Barwicz

Unoh Kwon

Gary Bela Bronner

James David Strom

Viorel C Ontalus

Philip Joseph Oldiges

Grant Paul Kesselring

Ashima B Chakravarti

Jerzy Maria Zalesinski

Diane Catherine Boyd

Deok-kee Kim

Effendi Leobandung

Stephen W Bedell

Rajiv V Joshi

Kevin K Chan

Haizhou Yin

Baozhen Li

Timothy Dooling Sullivan

Jack Oon Chu

Thomas N Adam

Richard Stephan Wise

Ronald G Filippi

Thomas M Shaw

Mark Alan Lavin

Rasit Onur Topaloglu

John Albrecht Ott

John Christopher Arnold

Paul Christian Parries

Tong Li

Rama Divakaruni

Amith Singhee

Fook-Luen Heng

Hiroyuki Akatsu

David S Wolpert

Jonathan R Fry

Steven Paul Ostrander

Michael Sperling

Anthony Gene Domenicucci

Rama Nand Singh

Emrah Acar

An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.

Short circuit detection in a read/write assist capacitor of a memory

A structure is provided that includes a first active circuit in which at least one of areas surrounding the first active circuit includes an active circuit-containing region. A second active circuit is spaced apart from the first active circuit. The second active circuit includes a circuit mimic fill area present in at least one of the areas surrounding the second active circuit. The circuit mimic fill area substantially matches the active circuit-containing region that is adjacent to the first active circuit. The circuit mimic fill area is located on an equivalent side of the second active circuit as the active circuit-containing region that is present adjacent the first active circuit. The use of the circuit mimic fill mitigates the effects over medium range and beyond distances that cause device failure.

Device mismatch mitigation for medium range and beyond distances

A method for production analysis includes: receiving production data at a processor from a plurality of tools spatially arranged within a manufacturing facility; creating a hierarchal topology of the data in the processor, wherein each level of the hierarchal topology is based on a different one of a plurality of static parameters that are selected from a list consisting of: a tool identifier, a batch identifier, and a spatial orientation; displaying, at a user interface implemented by the processor, a first analysis of a first level of the hierarchal topology, wherein the analysis contains parameters related to other levels of the hierarchal topology; receiving, via the user interface, a selection by a user of a first parameter displayed on the first analysis; and updating the user interface to display a second analysis of a second level of the hierarchal topology that is related to the first parameter.

Exploratory data interface

A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.

Stacked via rivets in chip hotspots

A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.

Multi-mode design and operation for transistor mismatch immunity

Methods and systems for a circuit similarity metric for semiconductor testsite coverage. One or more unique values for each of a set of measures for each circuit layout of a plurality of circuit layouts are identified and a pairwise comparison across the set of measures is conducted for a selected pair of the plurality of circuit layouts to derive a similarity score for the selected pair of circuit layouts. The similarity score is incremented for the selected pair in response to the selected pair of circuit layouts sharing a same unique value and the similarity score is decremented for the selected pair in response to one circuit layout of the selected pair of circuit layouts having a unique value that the other circuit layout of the selected pair does not contain.

Circuit layout similarity metric for semiconductor testsite coverage

A technique for optimizing integrated circuit (IC) designs based on interaction between multiple integration design rules is provided. For a plurality of IC features, total risk values are determined based on multiple integration design rules. IC features are ordered based on the total risk values. IC features having the highest total risk values are selected based on a threshold count. An IC design is clipped around the high-risk IC features. An overall failure rate is simulated for the clipped area. If the overall failure rate exceeds a threshold, a predicted failure rate for each design rule that applies to IC features within the clipped area is calculated. A high-risk design rule is identified based on the predicted failure rates. The IC design is modified such that a difference between a design rule value of the high-risk design rule and a corresponding design value is reduced.

Optimizing integrated circuit designs based on interactions between multiple integration design rules

Embodiments include method, systems and computer program products for designing physical devices using an iterative floorplan methodology. The method creating, using a processor, a rough floorplan, wherein the rough floorplan includes one or more tiles and estimates for one or more components associated with the floorplan. The processor converts the estimates for the one or more components to stresses and displacements/distortions associated with the one or more tiles. The processor further generates distortion data from the displacements/distortions associated with the one or more tiles. The processor further compares the distortion data to a threshold. The processor further creates a finalized floorplan based on the rough floorplan in response to the distortion data being below the threshold.

Deep trench floorplan distribution design methodology for semiconductor manufacturing

Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

Integrated circuit (IC) design analysis and feature extraction

In a system and method, a design layout defines a transistor, a local layout effect (LLE)-inducing feature and shapes, including a non-uniform shape, that illustrate separation between the channel region and LLE-inducing feature. Layout information for the non-uniform shape, including minimum and maximum distances between the channel region and LLE-inducing feature, is extracted. Based on this layout information, a first width of a first portion of the non-uniform shape, which is associated with the maximum distance, and a second width of a second portion of the non-uniform shape, which is associated with the minimum distance, are derived and used to calculate the non-uniform shape's contribution to the value of a model parameter adjuster. The value of the model parameter adjuster is then calculated based on a sum of contributions from all shapes and used to generate a compact model for modeling a performance attribute of the transistor within the IC.

Modeling transistor performance considering non-uniform local layout effects

Various embodiments include computer-implemented methods, computer program products and systems for modeling at least one feature in an integrated circuit (IC) layout for an inter-layer effect. In some cases, approaches include a computer-implemented method of modeling at least one feature in an IC layout for an inter-level effect, the method including: building a set of shape measurement regions each connected with an edge of the at least one feature; determining a set of shape parameters for each shape measurement region in the set of shape measurement regions; and creating a column vector representing each shape measurement region using the set of shape parameters, the column vector representing the inter-layer effect of the at least one feature, wherein the inter-layer effect includes a physical relationship between the at least one feature and another feature on a distinct level of the IC layout.

Optical proximity correction (OPC) accounting for critical dimension (CD) variation from inter-level effects

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a stressing layer on a substrate. The method may include doping the stressing layer with dopants. The method may include forming a silicide layer on the stressing layer. Moreover, the stressing layer may include a first lattice constant different from a second lattice constant of the substrate.

High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data.

Correcting for stress induced pattern shifts in semiconductor manufacturing

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Weston, CT, United States of America

Dureseti Chidambarrao