Texas Instruments Corporation

Duofeng Yue

Peijun Chen

Sue E Crank

Thomas Dyer Bonifield

Jiong-Ping Lu

Amitabh Jain

Homi C Mogul

Donald S Miles

Pinghai Hao

Fuchao Wang

Noel M Russell

Lance Stanford Robertson

Amitava Chatterjee

Stephan Grunow

Satyavolu Srinivas Papa Rao

Lindsey H Hall

Kaiping Liu

Song Zhao

Douglas E Mercer

Clint Montgomery

Jeffrey Loewecke

Jiejie Xu

Montray Leavy

Thomas Patrick Conroy

Xiaozhan Liu

Thomas D Bonifiield

Jie-Jie Xu

An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.

Single photomask high precision thin film resistor

The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

Nickel alloy silicide including indium and a method of manufacture therefor

The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device () , among other steps, includes forming a gate structure () over a substrate () and forming source/drain regions () in the substrate () proximate the gate structure (). The method further includes subjecting the gate structure () and substrate () to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains () subsequent to subjecting the gate structure () and substrate () to the dry etch process. Thereafter, the method includes forming metal silicide regions () in the gate structure () and the fluorinated source/drains ().

Method for manufacturing a semiconductor device having silicided regions

Methods () are described for calibrating the implantation angle of an ion implanter utilized in the manufacture of semiconductor products. One method () includes implanting () phosphorous ions into a pilot wafer held by a wafer platen held at a starting implantation angle in the ion implanter. The phosphorous implantation into a p-doped substrate of the pilot or blank wafer, for example, forms a semiconductive sheet. The method () then includes changing the implantation angle (), and implanting another wafer () with phosphorous ions. The angle changing () and implanting () of other wafers continues in this manner until all wafers or angles are implanted () as desired. The phosphorous implanted wafers are then measured () with a four-point probe, for example, to obtain the sheet resistance of all the implanted wafers. The difference between the sheet resistances of the wafers at each corresponding implant angle is then obtained () to determine a functional relationship between the sheet resistance and the implantation angle. Finally, the functional relationship is then used to calibrate () the implantation angle of the implanter. For example, the lowest sheet resistance of the functional relationship may be determined, the relationship normalized to the lowest sheet resistance, then a zero degree implantation angle of the implanter is calibrated to to coincide with the lowest sheet resistance measurement.

Method for implanter angle verification and calibration

The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (), as well as a nickel silicide region () located over the substrate (), the nickel silicide region () having an amount of indium located therein.

Nickel silicide including indium and a method of manufacture therefor

The present invention provides a method for forming an interconnect on a semiconductor substrate. The method includes forming an openingover an inner surface of the opening, the depositing forming a reentrant profile near a top portion of the opening. A portion of barrieris etched, which removes at least a portion of the barrierto reduce the reentrant profile. The etching also removes at least a portion of the barrierlayer at the bottom of the opening

Contact resistance reduction by new barrier stack process

Fluorine containing regions () are formed in the source and drain regions () of the MOS transistor. A metal layer () is formed over the fluorine containing regions () and the source and drain regions (). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.

Integrated circuit metal silicide method

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, halogen atoms () and transition metal atoms () to form a halogen-containing metal layer () on a semiconductor substrate (). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit () comprising the metal silicide electrode.

Metal-halogen physical vapor deposition for semiconductor device defect reduction

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises implanting small atoms into an nMOS semiconductor substrate () to a depth () no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer () over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit ().

Metal silicide induced lateral excessive encroachment reduction by silicon &#x3c;110&#x3e; channel stuffing

A method for forming metal silicide regions in source and drain regions () is described. Prior to the thermal annealing of the source and drain regions (), germanium is implanted into a semiconductor substrate adjacent to sidewall structures () formed adjacent gate structures (). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (). Following thermal annealing of the source and drain regions (), the implanted germanium prevents the formation of metal silicide spikes.

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Plano, TX, United States of America

Duofeng Yue