Micron Technology Incorporated

Marvell International Limited

Marvell Asia Pte., Ltd.

Marvellworld Trade Ltd.

Juniper Networks, Inc.

Chrontel Inc.

Dung Viet Nguyen

Phong Sy Nguyen

Shashi Kiran Chilappagari

James Fitzpatrick

Nedeljko Varnica

Kishore Kumar Muchherla

Tomoharu Tanaka

Huai-Yuan Tseng

Eric N Lee

Akira Goda

Sivagnanam Parthasarathy

Patrick Robert Khayat

Dave Scott Ebsen

Sampath K Ratnam

Shantilal Doru

Zhengang Chen

David Scott Ebsen

Christophe Therene

Vamsi Pavan Rayaprolu

Mustafa Nazmi Kaynak

Jun Wan

Timothy J Donovan

Steven Michael Kientz

Jeffrey S McNeil, Jr

Jack W Kohn

Boris Reynov

Shreeram Siddhaye

Eyal En Gad

Euan F Mowat

Giovanni Maria Paolucci

Zixiang Loh

Meng Long

Venkata Penmetsa

Ka-Ming Keung

Hope Abigail Henry

Thomas Herbert Lentz

Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.

Generating semi-soft bit data during corrective read operations in memory devices

Described are systems and methods for memory read calibration based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first metric characterizing threshold voltage distributions of a subset of the plurality of memory cells; determining a first read voltage adjustment; receiving a second metric characterizing the threshold voltage distributions; determining a second read voltage adjustment; and applying the second read voltage adjustment for reading the subset of the plurality of memory cells.

Memory read calibration based on memory device-originated metrics characterizing voltage distributions

Described are systems and methods for memory read threshold tracking based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first value of a metric characterizing threshold voltage distributions of a subset of a set of the plurality of memory cells; determining a first voltage threshold adjustment value; receiving a second value of the metric; determining a second voltage threshold adjustment value; and applying the second voltage threshold adjustment value for reading the set of the plurality of memory cells.

Memory read voltage threshold tracking based on memory device-originated metrics characterizing voltage distributions

Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.

Adaptive pre-read management in multi-pass programming

A method includes performing a read operation of a first codeword including first hard data and generating an error vector using a reliability metric of the first hard data. The first hard data and error vector are stored in first and second portions of memory. A first corrected codeword is returned that combines the error vector and the hard data from the first and second portions of memory. A read operation of a second codeword is performed, including second hard data and soft information. The hard data and soft information are stored in the first and second portions of memory. A bit of second hard data is flipped responsive to comparing a reliability metric of the bit of the second hard data to a bit flipping threshold, wherein flipping the bit includes updating the second hard data. The updated second codeword is returned resulting from reading the portions of memory.

Efficient memory use to support soft information in bit flipping decoders

In some implementations, a controller of a memory device may obtain a first metric associated with a memory of the memory device using a first memory read configuration. The controller may apply a function to the first metric to obtain a second memory read configuration. The controller may obtain a second metric associated with the memory using the second memory read configuration. The controller may filter the first metric and the second metric to obtain a first filtered metric and a second filtered metric. The controller may provide the first filtered metric and the second filtered metric to a memory management process executing on the controller. The controller may perform an action based on an output of the memory management process, wherein the output is based on the first filtered metric and the second filtered metric.

Filtering metrics associated with memory

A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Memory device programming technique for increased bits per cell

A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices

A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

Conditional valley tracking during corrective reads

Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same

Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Quick charge loss mitigation using two-pass controlled delay

A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.

Accessing data using error correction operation(s) to reduce latency at a memory sub-system

A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.

Memory device programming technique using fewer latches

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San Jose, CA, United States of America

Dung Viet Nguyen