International Business Machines Corporation

Dell Products Inc.

Dung Q Nguyen

Hung Qui Le

Brian William Thompto

Sundeep Chadha

Brian David Barrick

Susan Elizabeth Eisen

David R Terry

Steven J Battle

Joshua W Bowman

Michael Joseph Genden

Salma Ayub

Maureen Anne Delaney

Cliff Kucharski

Jeffrey Carl Brownscheidle

Kenneth Lundy Ward

Christopher Michael Abernathy

Mary Douglass Brown

Dhivya Jeganathan

Christopher M Mueller

James Wilson Bishop

Benjamin W Stolt

Kurt Alan Feiste

Jentje Leenstra

Balaram Sinharoy

David Allen Hrusecky

Albert James Van Norstrand, Jr

Robert Allen Cordes

Tu-An T Nguyen

Richard James Eickemeyer

Brandon R Goddard

Sam G Chu

Eula A Tolentino

Saiful Islam

Jing Zhang

Bryan J Lloyd

Glenn Owen Kincaid

Jose Eduardo Moreira

Maarten Jakob Boersma

Salim Ahmed Shah

Raymond Cheung Yeung

Jafar Nahidi

William Elton Burky

Jose Angel Paredes

Deepak K Singh

John Barry Griswell, Jr

Niels Fricke

Christian Zoellin

Nicholas R Orzol

James Allan Kahle

Sheldon Bernard Levenstein

Sam Gat-Shang Chu

Owen Chiang

Marcy Evelyn Byers

Markus Kaltenbach

Phillip G Williams

Joe Lee

David Scott Ray

Andreas Wagner

Joel Abraham Silberman

Gregory William Alexander

Scott Barnett Swaney

Shih-Hsiung Stephen Tung

David Andrew Schroter

Michael Klaus Kroener

Albert Thomas Williams

Michael James Mack

Eric M Schwarz

Silvia Melitta Mueller

Michael Stephen Floyd

David Arnold Luick

Brian William Curran

Todd Alan Venton

Michael Thomas Vaden

Robert Greg McDonald

Mehul N Patel

David Wayne Victor

Jessica Hui-Chun Tseng

Gaurav Mittal

Ophir Erez

Alper Buyuktosunoglu

Pradip Bose

Manoj N Kumar

Pratap Chandra Pattnaik

Kattamuri Ekanadham

Alexander Erik Mericas

Brian R Konigsburg

Hoichi Cheong

Jens Leenstra

Bruce Joseph Ronchetti

Brian Robert Mestan

Juergen Haess

Philip Lee Vitale

Nicolas Maeding

Razvan Peter Figuli

Taqi Nasser Buti

Edmund Joseph Gieske

Lawrence Joseph Powell, Jr

Robert Dominick Mirabella

Kin Shing Chan

Scott Michael Ramsey

A system, processor, programming product and/or method for assigning instructions to destination register file blocks, and/or routing instructions, includes: providing a processing pipeline having two or more execution units configured to process instructions; providing a register file having register file entries configured to hold data, where the register file is subdivided into a plurality of register blocks and each register block has two or more register file entries; calculating a utilization rate for one or more register blocks; and assigning and/or routing an instruction to write its results to a register block based upon the utilization rate for that register block. Preferably the execution unit is configured to write its results to a single specific destination (rename) register block.

Routing instruction results to a register block of a subdivided register file based on register block utilization rate

An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries

Provided is a method for assigning register tags to instructions at issue time. The method comprises receiving an instruction for execution by a microprocessor. The method further comprises dispatching the instruction to an issue queue without assigning a register tag to the instruction. The method further comprises determining that the instruction is ready to issue. In response to determining that the instruction is ready to issue, the method comprises assigning an available register tag to the instruction. The method further comprises issuing the instruction.

Assignment of microprocessor register tags at issue time

A method for restoring a mapper of a processor core includes saving first information in a staging latch. The first information represents a newly dispatched first instruction of the processor core and is saved in an entry latch of a save-and-restore buffer. In response to reception of a flush command of the processor core, the restoration of the mapper is begun with the first information from the staging latch without waiting for a comparison of a flush tag of the flush command with the entry latch of the save-and-restore buffer. A processor core configured to perform the method described above is also provided. A processor core is also provided that includes a dispatch, a mapper, a save-and-restore buffer that includes entry latches and is connected to the mapper via at least one pipeline, and a register disposed in the at least one pipeline.

Fast mapper restore for flush in processor

A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with a single register tag, write the register tag into a mapper with bits indicating that the register tag is for a first instruction of the two instructions, write the register tag into the mapper with bits indicating that the register tag is for a second instruction of the two instructions, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation units (VSU), and execute the two instructions.

Loosely-coupled slice target file data

A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.

Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction

A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.

Inferring future value for speculative branch resolution in a microprocessor

Disclosed is a method for rebalancing blocks of a register file. The method comprises allocating a first set of entries in a first register file to a first hardware thread of a processor core. The method further comprises allocating a second set of entries in a second register file to a second hardware thread of the processor core. The register tags in the first and second register files are compacted such that register tags associated with the first hardware thread are compacted into the first set of entries, and register tags associated with the second hardware thread are compacted into the second set of entries.

Compaction of architected registers in a simultaneous multithreading processor

A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Instruction handling for accumulation of register results in a microprocessor

Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.

Microprocessor that fuses load and compare instructions

Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.

Inferring future value for speculative branch resolution

A computer processor includes a dispatch stage and a dependency skipping execution unit. The dispatch stage is configured to dispatch a plurality of instructions that include a general purpose instruction configured to produce first data, a dependent instruction configured to produce second data, and an indirect dependent instruction configured to produce third data. The dependency skipping execution unit is configured to monitor the plurality of instructions and to process the indirect dependent instruction in response to the general purpose instruction producing the first data. The indirect dependent instruction is issued independently from the second data produced by the indirect dependent instruction.

Dependency skipping execution

A processor includes a first level register file, second level register file, and register file mapper. The first and second level register files are comprised of physical registers, with the first level register file more efficiently accessed relative to the second level register file. The register file mapper is coupled with the first and second level register files. The register file mapper comprises a mapping structure and register file mapper controller. The mapping structure hosts mappings between logical registers and physical registers of the first level register file. The register file mapper controller determines whether to map a destination logical register of an instruction to a physical register in the first level register file. The register file mapper controller also determines, based on metadata associated with the instruction, whether to write data associated with the destination logical register to one of the physical registers of the second level register file.

Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file

A computer system, processor, programming instructions and/or method of processing data that includes a main register file having a plurality of entries for storing data; an accumulator register file having a plurality of entries for storing data wherein multiple main register file entries are mapped to one accumulator register file entry in the at least one accumulator register file; a logical register mapper to track and map logical registers to main register file entries, and a history buffer. Processing wide data width instructions includes evicting and restoring information from a single primary entry in the logical register mapper through a single read or write port in the logical register mapper without evicting or restoring the remaining other multiple main register file entries mapped in the accumulator register.

Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry

Growing community of inventors

Austin, TX, United States of America

Dung Q Nguyen