Cypress Semiconductor Corporation

Dung Ho

Sungkwon Lee

Timothy John Williams

Eric N Mann

Toru Miyamae

Ravindra Manohar Kapre

David Michael Rogers

Eric Lee Swindlehurst

Yan Yi

Ryuta Nagai

Mimi Xuefeng Zhao Qian

Boo Chin-Hua

Andrew J Walker

Roger J Bettman

Sai Prashanth Dhanraj

Leo F Luquette, Jr

Iman Rezanezhad Gatabi

An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

ESD protection circuit

An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.

ESD clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage

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Sunnyvale, CA, United States of America

Dung Ho