Motorola Corporation

Mindspeed Technologies, Inc.

Duncan M Fisher

Tan Nhat Dao

Rajiv Gupta

Keith M Bindloss

Joseph B Tompkins

Brian T Kelley

Jeffrey L Klein

Marty T Budrovic

John E VanderMeer

Ching Long Su

An alternate multi-thread pipeline structure and method are provided. A deep pipeline is provided in which two threads of two separate pipeline stages are alternatively presented to the various logic and latch circuits for execution. The execution and latching of the threads alternates from one thread to the other within a single clock cycle. Thus, each thread is executed once per clock cycle and two threads are executed in a single clock cycle.

Method and system for execution and latching of data in alternate threads

Various systems and methods for error correction of instructions in an instruction cache coupled to a processor are provided. In one embodiment, a plurality of instructions stored in the instruction cache are fetched for execution by the processor, each of the instructions being fetched during a respective one of a plurality of instruction cycles of the processor. Error detection is performed for each of the instructions concurrently with the fetching of a respective one of the instructions.

Error correction in a cache memory

According to one embodiment, a RAM array includes at least one RAM cell comprising a first access transistor driven by a first word line. When the first access transistor is turned on, it couples the RAM cell to a first bit line. The first bit line is connected to a single-ended sense amplifier such as an inverter. Similarly, the RAM cell comprises second, third, and fourth access transistors driven by respectively second, third, and fourth word lines. When the respective access transistors are turned on, they couple the RAM cell to respectively second, third, and fourth bit lines. The bit lines are connected to respective single-ended sense amplifiers such as inverters. In one embodiment, each of the first, second, third, and fourth access transistors is an NFET. The first, second, third, and fourth bit lines are coupled to respectively first, second, third, and fourth precharge transistors.

Four port RAM cell

Data block identification within a processor 100 may be accomplished when the processor 100 receives an interrupt while performing a main set of operational codes. Upon receiving the interrupt, the processor 100 determines whether the interrupt is of a fast interrupt type. When the interrupt if of a fast interrupt type, the processor executes the operational codes identified by the interrupt without having to flag the main set of operational codes. Upon completion of the fast interrupt, the processor 100 resumes performing the main set of operational codes. In addition to performing the fast interrupt, the processor 100 contemporaneously performs a data block identification routine. When the data block identification routine identifies a data block, the main set of operational codes is interrupted to perform a data block service routine. The processor 100 includes an address generation unit 102 and a peripheral address generation unit 104. The peripheral address generation unit 104 will provide addresses for storing data samples in a data memory 103 in response to an interrupt request when address generation unit 102 does not have an available address register 113.

Address generation apparatus and method using a peripheral address

A method and apparatus for an improving memory access bandwidth that can be used in a digital signal processor (DSP) (500) is accomplished by modifying addresses (302, 304) generated by an address generation unit (AGU) (102) of the DSP (500). Two addresses (302, 304) are generated by the AGU (102). One of the two addresses (302) is used to address two parallel memory blocks (308, 310) in a single memory simultaneously, and the other address (304) is modified by a modulo increment function to produce two additional addresses (404, 406) that also address the parallel memory blocks (308, 310). With such a method and apparatus, four simultaneous memory reads can occur, effectively doubling the memory access bandwidth in the DSP system (500) without modification of the AGU (102) or program controller (510).

Method and apparatus utilizing simultaneous memory reads for increasing

A data processing system (10) and associated method (150) of operation selectively compand data on a slot-by-slot basis. The data processing system (10) includes a processor (12), processor bus (14), memory (16), output serial interface (18), and input serial interface (70). The output serial interface (18) includes an output data buffer (20), compression module (22), output shift register (24), and output controller (26). In operation, the output serial interface (18) receives output data (28) and selectively compresses the data on a slot-by-slot basis. The shift register (24) then places the transmit data (32) on the serial link (25). An input serial interface (128) selectively expands data received on the serial link (25) on a slot-by-slot basis to produce input data (82). The associated method (150) includes method steps for companding data on a slot-by-slot basis. An ISDN interface and digital telephone (200) employ the teachings of the present invention.

Apparatus and method for selectively companding data on a slot-by-slot

A process for forming a via in a semiconductor device using a self-aligned metal pillar to connect metal layers separated by a dielectric. A first aluminum layer is formed on an oxide layer overlying a semiconductor substrate, and a thin tungsten layer is formed and patterned overlying the first aluminum layer. The pattern in this tungsten layer will determine the pattern for the first level of metal interconnect to be formed later in the first aluminum layer. The tungsten layer is etched using the underlying first aluminum layer as an etch stop. A second aluminum layer is then formed overlying the patterned tungsten layer and the exposed regions of the first aluminum layer. In one continuous etching step the second aluminum layer is patterned and etched to form a pillar, and the first aluminum layer is etched to form the first level of metal interconnect in the semiconductor device using the pattern formed earlier in the tungsten layer and to expose regions of the oxide layer. A dielectric is deposited overlying the exposed regions of the oxide layer, the formed pillar, and the thin tungsten layer. This dielectric is etched back to expose the top of the pillar, and then a third aluminum layer is deposited overlying the dielectric to make electrical contact to the exposed surface of the pillar.

Growing community of inventors

Mission Viejo, CA, United States of America

Duncan M Fisher