Kioxia Corporation

Lsi Corporation

Plx Technology, Inc.

Duncan Beadnell

Neil Buxton

Don Harwood

Francesco Forte

Gary Calder

The present invention pertains to a method of verifying a design of an integrated circuit. The methods executes an iteration of simulation test cycle using a digital representation of the design. Next, the method obtains simulation results from the iteration of the simulation test cycle and calculates, during the simulation test cycle, a test coverage value associated with the simulation results of the iteration of the simulation test cycle. If the test coverage value is less than a target value, the method determines if the simulation test cycle fails to satisfies an iteration limiting metric. If the simulation test cycle satisfies the iteration limiting metric, the method, dynamically adjusts one or more simulation test cycle parameter during the simulation test cycle and iterates the simulation test cycle and recalculating the test coverage value until the test coverage value is at least the target value or the simulation test cycle fails to satisfy the iteration limiting metric. The method then out puts a result of the verification of the design.

Enhanced coverage convergence and test status during simulation runtime

A storage system stores data in at least one partition of a physical storage media in accordance with file system information specifying a plurality of logical blocks having logical block addresses within the partition. The logical blocks include excess logical blocks that are not mapped to space in the physical storage media by the mapping employed by the storage system. Unusable block data marks those excess logical blocks as unusable. This makes it easy to adjust the data storage capacity of the storage system by changing the mapping to map more or less logical block addresses to space in the physical storage media and thereby destroy or create excess logical blocks, and by changing the unusable block data to correspondingly change the excess logical blocks marked as unusable.

Adjustment of data storage capacity provided by a storage system

A bridge device for connecting a USB 3 host device with a plurality of downstream, non-USB 3 mass storage devices, such as SATA or PATA devices. The bridge device comprises an embedded hub having a plurality of internal USB 3 devices. The internal USB 3 devices do not have a physical USB 3 interface. The bridge device also has at least one downstream physical non-USB 3 device, to which a mass storage device may be attached. The internal USB 3 devices enable the host device to be presented with a plurality of USB 3 devices. This, in turn, allows transfer to the plurality of downstream physical non-USB 3 devices, via the internal USB 3 devices at an increased rate. The bridge may also include a downstream physical USB 3 interface. This can allow multiple bridge devices to be connected together in a cascade.

Growing community of inventors

Abingdon, United Kingdom

Duncan Beadnell