Nvidia Corporation

Nvdia Corporation

Duncan Andrew Riach

Michael A Ogrinc

Brijesh Tripathi

Leslie E Neft

Tyvis Cheung

Wayne D Young

Henry Packard Moreton

Jonah Matthew Alben

Patrick Rene Marchand

Robert Anthony Alfieri

John M Danskin

Hassane S Azar

Anthony Michael Tamasi

Wayne Douglas Young

Douglas H Rogers

Michael B Nagy

Douglas Sim Dietrich, Jr

Alvin Ihsani

Apparatuses, systems, and techniques to deterministically classify data. In at least one embodiment, inference classes with weights within a threshold range are treated as equivalent and one representative inference class is selected.

Tie-breaker for inference reproducibility

One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.

Multiple simultaneous unique outputs from a single display pipeline

One embodiment of the present invention sets forth a technique for controlling mode switches in hardware. The resource manager includes an 'is mode possible' function that evaluates a given mode in conjunction with the limitations of the hardware to determine if the given mode is feasible. The display driver is configured to call this function to validate a proposed mode before generating commands specifying the state changes for the display heads. The display software interface hardware module within the GPU processes these commands and follows a standard sequence of steps to implement the mode switch. The steps may include interrupts to the resource manager to re-validate the proposed mode, again calling the 'is mode possible' function, or perform operations that are not yet supported in the hardware. Advantageously, controlling mode switches in hardware enables less error-prone, more efficient, and more discerning mode switches relative to controlling mode switches in software.

System and method for controlling mode switches in hardware

One embodiment of the invention sets forth a method for transmitting display data to a display device. The method includes the steps of receiving a contract for a frame of display data, preparing the frame of display data to ensure the timing requirements of the display device can be satisfied based on the contract, and transmitting the frame of display data to the display device while the contract is pending.

Isochronous hub contracts

A method of displaying an image includes generating a contract in the display engine, transferring the contract to the memory controller before the end of a sweep, generating a contract amendment in response to changes in the display engine, transferring the contract amendment to the memory controller, making a decision whether the contract amendment can be processed, fetching data from the memory controller according to the contract incorporating the contract amendment if the decision is that the contract amendment can be processed, sending the fetched data to the display engine in an isochronous stream; and processing the fetched data using the display engine.

Contract based memory management for isochronous streams

One embodiment of the present invention sets forth a system for computing and error checking configuration parameters related to raster image generation within a graphics processing unit. Input parameters are validated by a hardware-based error checking engine. A hardware-based pre-calculation engine uses validated input parameters to compute additional private configuration parameters used by the raster image generation circuitry within a graphics processing unit.

Active raster composition and error checking in hardware

One embodiment of the present invention sets forth a protocol for packing and transferring pixel data between integrated circuits. The data transfer protocol may be used between a graphics processing unit and a video output encoder unit. The data transfers may include up to 20 pixels per arbitration cycle. By packing pixel data for transfer over a bus with a relatively small set of output pins, overall package pin count is reduced, while maintaining sufficient bandwidth to carry the pixel data the output pins. By moving the analog circuitry to a separate device, linked to the GPU via the bus, noise from the GPU may be effectively mitigate through physical separation.

Bus protocol for transferring pixel data between chips

An isochronous processor includes a state register, a functional unit, a control module, and an activation unit. The state register includes an arm buffer and an active buffer. The functional unit performs a transformation operation on the data stream in response to an active value of the control parameter obtained from the active buffer. The control module updates the arm value of the control parameter in the arm buffer in response to control instructions. The activation unit detects a load event propagating with the data stream and transfers the parameter value from the arm buffer to the active buffer in response to the load event. During this transfer, the control module is inhibited from updating the arm buffer.

Isochronous pipelined processor with deterministic control

A system and method for enabling or disabling clocks to one or more portions of hardware circuitry, for example a display sub-system of a personal computer. A processor generates a command or data to a first circuit configured to perform a function based at least on the command or data. A clock generator selectively supplies clocks to the first circuit and a second circuit configured to perform a second function. A software interface circuit coupled to the processor and the clock generator autonomously determines based at least on the command or data whether the second circuit will perform the second function or be idle in an upcoming period and disables one or more of the clocks to the second circuit if the second circuit will be idle in the upcoming period.

Work based clock management for display sub-system

In a graphics processor, a rendering object and a post-processing object share access to a host processor with a programmable execution core. The rendering object generates fragment data for an image from geometry data. The post-processing object operates to generate a frame of pixel data from the fragment data and to store the pixel data in a frame buffer. In parallel with operations of the host processor, a scanout engine reads pixel data for a previously generated frame and supplies the pixel data to a display device. The scanout engine periodically triggers the host processor to operate the post-processing object to generate the next frame. Timing between the scanout engine and the post-processing object can be controlled such that the next frame to be displayed is ready in a frame buffer when the scanout engine finishes reading a current frame.

Growing community of inventors

Mountain View, CA, United States of America

Duncan Andrew Riach