Omnivision Technologies, Inc.

Omnivision Technologies, Inc.omnivision Technologies, Inc.

Duli Mao

Gang Chen

Hsin-Chih Tai

Vincent Venezia

Howard E Rhodes

Dyson Hsinchih Tai

Yin Qian

Dajiang Yang

Bill Phan

Yuanwei Zheng

Sohei Manabe

Keiji Mabuchi

Qin Wang

Oray Orkun Cellek

Yuanliang Liu

Xin Ru Wang

Chih-Wei Hsiung

Ashish A Shah

Keh-Chiang Ku

Lindsay Alexander Grant

Zhiqiang Lin

Sing-Chung Hu

Cunyu Yang

Wei Zheng

Chen-Wei Lu

Arvind Kumar

Seong Yeol Mun

Dyson Hsin-Chih Tai

Bowei Zhang

Zhenhong Fu

Siguang Ma

Tiejun Dai

Hui Zang

Rongsheng Yang

Alireza Bonakdar

Xianmin Yi

Wei Dong Qian

Guannan Chen

Yi Ma

Boyd Fowler

Eric A G Webster

Johannes Solhusvik

Hidetoshi Nozaki

Chengming Liu

Trygve Willassen

Lequn Liu

Eric Webster

Zhibin Xiong

Hiroaki Ebihara

Zheng Yang

Jin Li

Shiyu Sun

Eiichi Funatsu

Dominic Massetti

Kevin W Johnson

Chia-Chun Miao

Hongli Yang

Woon Il Choi

Zhiyong Zhan

Manoj Bikumandla

Qingwei Shan

Kazufumi Watanabe

Takayuki Goto

Qingfei Chen

Heesoo Kang

Philip John Cizdziel

Yifei Du

Lingtao Jiang

WeiDong Qian

Han Lei Lock

Jens Landgraf

Dyson Hsinchin Tai

Takeshi Takeda

Dajing Yang

Xianfu Cheng

Jingming Yao

Hung Chih Chang

Hsin Chih Tai

Image sensors with improved memory effect are disclosed herein. In one embodiment, a method for reducing image lag associated with a pixel included in a plurality of pixels is described. The pixel includes a photodiode, a first floating diffusion coupled to the photodiode through a transfer transistor, a second floating diffusion coupled to the first floating diffusion through a dual floating diffusion transistor, and a lateral overflow integration capacitor coupled between the second floating diffusion and a bias voltage source. The lateral overflow integration capacitor is further coupled to a pixel reference voltage source through a reset transistor. Operation of the pixel comprises an idle period and an integration period after the idle period. The method also includes configuring the lateral overflow integration capacitor to be either zero-biased or forward-biased during the idle period.

Operation method to mitigate lag issue with high k metal-insulator-metal (MIM) capacitor

CMOS image sensor with multiple sensitivities for high dynamic range imaging and LED flicker mitigation. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Each pixel includes a plurality of cells. A plurality of color filters is disposed over corresponding plurality of cells. The plurality of color filters corresponding to the plurality of cells of an individual pixel have more than one filtering strength for each color of the plurality of color filters.

CMOS image sensor with multiple sensitivities for high dynamic range imaging and led flicker mitigation

Image sensors, isolation structures, and techniques of fabrication are provided. An image sensor includes a source of electromagnetic radiation disposed on a substrate, a pixel array disposed on the substrate and thermally coupled with source of electromagnetic radiation, and an isolation structure disposed on the substrate between the source of electromagnetic radiation and the pixel array. The isolation structure can define a first reflective surface oriented on a first bias relative to a lateral axis of the pixel array and a second reflective surface oriented on a second bias relative to the lateral axis. The isolation structure can be configured to attenuate residual electromagnetic radiation reaching a proximal region of the pixel array by pairing a first reflection and a second reflection of the electromagnetic radiation by the first reflective surface and the second reflective surface.

Image sensor diagonal isolation structures

A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A plurality of capacitor-switch pairs is coupled between the reset transistor and a bias voltage source. Each of the plurality of capacitor-switch pairs includes a lateral overflow integration capacitor (LOFIC) and a switch transistor coupled to the LOFIC.

High K metal-insulator-metal (MIM) capacitor network for lag mitigation

A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a pixel voltage source and the floating diffusion. A lateral overflow integration capacitor (LOFIC) network includes a first LOFIC coupled between the floating diffusion and the first bias voltage source, and a second LOFIC coupled between the floating diffusion and the second bias voltage source. The first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased at an end of an integration period, and image charge discharged from the first LOFIC and image charge discharged from the second LOFIC compensate each other during a readout period.

Optimized pixel design for mitigating MIM image lag

A reduced cross-talk pixel-array substrate includes a semiconductor substrate, a buffer layer, a metal annulus, and an attenuation layer. The semiconductor substrate includes a first photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the first photodiode region in a cross-sectional plane parallel to a first back-surface region of the back surface above the first photodiode region. The buffer layer is on the back surface and has a feature located above the first photodiode region with the feature being one of a recess and an aperture. The metal annulus is on the buffer layer and covers the trench. The attenuation layer is above the first photodiode region.

Suppressed cross-talk pixel-array substrate and fabrication method

An image sensor comprises a first photodiode region and circuitry. The first photodiode region is disposed within a semiconductor substrate proximate to a first side of the semiconductor substrate to form a first pixel. The first photodiode region includes a first segment coupled to a second segment. The circuitry includes at least a first electrode associated with a first transistor. The first electrode is disposed, at least in part, between the first segment and the second segment of the first photodiode region such that the circuity is at least partially surrounded by the first photodiode region when viewed from the first side of the semiconductor substrate.

Pixel layout with photodiode region partially surrounding circuitry

CMOS image sensor with LED flickering reduction and low color cross-talk are disclosed. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Each pixel includes a plurality of large subpixels (LPDs) and at least one small subpixel (SPD). A plurality of color filters are disposed over individual subpixels. Each individual SPD is laterally adjacent to at least one other SPD.

CMOS image sensor with LED flickering reduction and low color cross-talk

An image sensor includes a substrate. An array of photodiodes is disposed in the substrate. A plurality of spacers is arranged in a spacer pattern. At least one spacer of the plurality of spacers has an aspect ratio of 18:1 or greater. A buffer layer is disposed between the substrate and the spacer pattern. An array of color filters is disposed in the spacer pattern.

Fully buried color filter array of image sensor

A flicker-mitigating pixel-array substrate includes a semiconductor substrate and a metal annulus. The semiconductor substrate includes a small-photodiode region. A back surface of the semiconductor substrate forms a trench surrounding the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region. The metal annulus (i) at least partially fills the trench, (ii) surrounds the small-photodiode region in the cross-sectional plane, and (iii) extends above the back surface. A method for fabricating a flicker-mitigating pixel-array substrate includes forming a metal layer (i) in a trench that surrounds the small-photodiode region in a cross-sectional plane parallel to a back-surface region of the back surface above the small-photodiode region and (ii) on the back-surface region. The method also includes decreasing a thickness of an above-diode section of the metal layer located above the back-surface region.

Flicker-mitigating pixel-array substrate

A pixel cell includes a plurality of subpixels to generate image charge in response to incident light. The subpixels include an inner subpixel laterally surrounded by outer subpixels. A first plurality of transfer gates disposed proximate to the inner subpixel and a first grouping of outer subpixels. A first floating diffusion is coupled to receive the image charge from the first grouping of outer subpixels through a first plurality of transfer gates. A second plurality of transfer gates disposed proximate to the inner subpixel and the second grouping of outer subpixels. A second floating diffusion disposed in the semiconductor material and coupled to receive the image charge from each one of the second grouping of outer subpixels through the second plurality of transfer gates. The image charge in the inner subpixel is received by the first, second, or both floating diffusions through respective transfer gates.

High dynamic range split pixel CMOS image sensor with low color crosstalk

Image sensors include a substrate material having a plurality of small photodiodes (SPDs) and a plurality of large photodiodes (LPDs) disposed therein. A plurality of pixel isolators is formed in the substrate material, each pixel isolator being disposed between one of the SPDs and one of the LPDs. A passivation layer is disposed on the substrate material and a buffer layer is disposed on the passivation layer. A plurality of first metal elements is disposed in the buffer layer, each first metal element being disposed over one of the pixel isolators, and a plurality of second metal elements is disposed over the plurality of first metal elements.

Method and structure to improve image sensor crosstalk

A pixel cell includes a first photodiode, a second photodiode, a first deep trench isolation region, a second deep trench isolation region, a buffer oxide layer, and a light attenuation layer. The attenuation layer partially encapsulates the first photodiode by extending laterally from the first deep trench isolation region to the second deep trench isolation region between the semiconductor material and the buffer oxide layer.

Image sensor with partially encapsulating attenuation layer

An image sensor includes a substrate material. The substrate material includes a plurality of photodiodes disposed therein. The plurality of photodiodes includes a plurality of small photodiodes (SPDs) and a plurality of large photodiodes (LPDs) larger than the SPDs. An array of color filters is disposed over the substrate material. A buffer layer is disposed between the substrate material and the array of color filters. A metal pattern is disposed between the color filters in the array of color filters, and between the array of color filters and the buffer layer. An attenuation layer is disposed between the substrate material and the array of color filters. The attenuation layer is above and aligned with the plurality of SPDs and a portion of each of the plurality of LPDs. An edge of the attenuation layer is over one of the plurality of LPDs.

Image sensor with split pixel structure and method of manufacturing thereof

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Sunnyvale, CA, United States of America

Duli Mao