Dell Products Inc.

Other

Duk Moon Kim

Shyamkumar Thiyagarajan Iyer

Srikrishna Ramaswamy

Gaurav Chawla

Isaac Qin Wang

Shyam T Iyer

Timothy Michael Lambert

Robert Wayne Hormuth

Johan Rahardjo

Jeremiah James Bartlett

Joshua David Anderson

Nelson Mak

An information handling system includes first and second devices, a connectivity switch, and a baseboard management controller. The first and second devices are configured to communicate with first and second processors of the information handling system. The connectivity switch is connected between the first and second devices and the first and second processors. The connectivity switch operates in one of a plurality of configurations including a first configuration, a second configuration, and a third configuration. Each of the configurations provides a different connectivity between the first device, the second device, the first processor, and the second processor. The baseboard management controller determines a setup of the first and second devices, and provides a connectivity indication signal to the connectivity switch based on the setup of the first and second devices. The connectivity indication signal identifies one of the configurations for the connectivity switch.

System and method for high configurability high-speed interconnect

An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.

System and method for controlling a power-on sequence and power throttling using power brake

In one or more embodiments, one or more systems, methods, and/or processes may determine a Peripheral Component Interconnect Express (PCIe) endpoint, associated with a PCIe destination endpoint identification, includes a field programmable gate array (FPGA); may access a partial configuration for the FPGA; may construct multiple packets that include the PCIe destination endpoint identification and respective portions of the partial configuration for the FPGA; and may provide the multiple packets to the PCIe endpoint. In one or more embodiments, the one or more systems, methods, and/or processes may further map at least a portion of the FPGA to a virtual machine. In one or more embodiments, the one or more systems, methods, and/or processes may further combine the portions of the partial configuration for the FPGA to reconstruct the partial configuration for the FPGA; and may further program the FPGA with the partial configuration for the FPGA.

System and method of configuring field programmable logic arrays

An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory transaction request from a first peripheral component interconnect express (PCIe) device to a system memory. The first memory transaction request includes a first system memory address. A second memory transaction request is detected from a second PCIe device to the system memory. The second memory transaction request includes a second system memory address. The method further includes determining if the first system memory address and the second system memory address are the same system memory address. In response to the first and second system memory addresses being the same, the first memory transaction request and the second memory transaction request are coalesced into a common memory transaction request. The common memory transaction request is issued to the system memory.

System and method for improving peripheral component interface express bus performance in an information handling system

In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.

Systems and methods for hardware-based RAID acceleration

In accordance with embodiments of the present disclosure, an information handling system may include a processor subsystem having access to a memory subsystem and a device communicatively coupled to the processor subsystem, the device having an endpoint assigned for access by an operating system executing on the processor subsystem such that the endpoint appears to the operating system as a logical hardware adapter, wherein the device is configured to discover a private device coupled to the device, enumerate the private device as a managed device of the device, and map a portion of a virtual address space of an operating system executing on the processor subsystem to the private device, such that the private device is abstracted to the operating system as a virtual memory address of the operating system.

Systems and methods for discovering private devices coupled to a hardware accelerator

Methods and systems for I/O acceleration using an I/O accelerator device on a virtualized information handling system include pre-boot configuration of first and second device endpoints that appear as independent devices. After loading a storage virtual appliance that has exclusive access to the second device endpoint, a hypervisor may detect and load drivers for the first device endpoint. The storage virtual appliance may then initiate data transfer I/O operations using the I/O accelerator device. The data transfer operations may be read or write operations to a storage device that the storage virtual appliance provides access to. The I/O accelerator device may use direct memory access (DMA).

System and method for input/output acceleration device having storage virtual appliance (SVA) using root of PCI-E endpoint

A mailbox includes a housing for receiving and storing mail, the housing having a first upper opening through which mail can be deposited and retrieved, and a second lower opening through which mail can be retrieved; a mailbox door mounted to the housing for movement between a first door position in covering relation to the first opening and a second door position out of the covering relation; and a lockable door movable between a first locked position in covering relation to the second opening and a second unlocked position out of the covering relation to permit access to the housing. A mail support is movably mounted within the housing for movement between a first mail support position for supporting mail adjacent the first opening and a second position for supplying mail to a lower portion of the housing adjacent the second opening. A lower support is movably mounted within the housing for movement between a first support position to prevent the mail support from moving to the second position, in response to movement of the mailbox door to the second door position, and a second position out of engagement with the mail support so as to release the mail support so that the mail support can move to the second position thereof, in response to movement of the mailbox door to the first door position. A support member is provided for releasably retaining the mail support in the first mail support position, regardless of the position of the mailbox door and the lower support.

Mailbox with mail storage and theft prevention

A combined cycle cogeneration power plant includes a combustion turbine formed by an inlet for receiving fuel, an inlet for receiving air, a combustor for burning the combustion fuel and the air, and an outlet through which hot gaseous combustion product is released; a regenerative fuel heating system formed by a plurality of heat exchangers for transferring heat to combustion fuel for heating the combustion fuel, and modulating control valves for controlling temperature of the combustion fuel; a heat recovery steam generator (HRSG) connected to the outlet of the combustion turbine for receiving the gaseous combustion product. The HRSG is formed by a plurality of heat exchangers including steam/water drums, each having a surface blowdown connection, and evaporators connected to the steam/water drums, a water inlet connected with the heat exchangers of the HRSG, a steam outlet, and a stack for releasing the exhausted gaseous combustion product. A steam turbine is provided, and has a steam inlet for receiving steam from the steam outlet of the HRSG, and an exhaust steam outlet; a condenser is connected to the exhaust steam outlet of the steam turbine for condensing steam to a liquid condensate; at least one pump is provided for supplying the liquid condensate from the condenser to the HRSG; and at least one pump is provided for supplying feed water from at least one drum to the HRSG. A conventional-type power plant with a regenerative fuel heating system is also disclosed.

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Cedar Park, TX, United States of America

Duk Moon Kim