Magnachip Semiconductor, Inc.

Hynix Semiconductor Inc.

Duk Ju Jeong

Young Chul Seo

Kee Sik Ahn

Sung Bum Park

Su Jin Kim

Tae Woo Kwon

Provided is a circuit for generating a bias current, which includes a current generation unit including a plurality of current mirrors that generate a plurality of currents having different levels. The circuit also includes a current generation control unit that controls the generating the plurality of current having different levels in the current generation unit based on an externally input current. The circuit further includes a current supplying unit that supplies a current selected from the plurality of currents having different levels to an external device.

Circuit for generating bias current for reading OTP cell and control method thereof

A power switch circuit comprises a first level shifter configured to turn on a first switching element configured to receive a supply voltage from an external voltage supply pad in response to a program operation of a one-time programmable (OTP) memory cell array, a second level shifter configured to turn on a second switching element and provide the supply voltage to the OTP memory cell array in response to the program operation, a third level shifter configured to turn on a third switching element and provide an internally generated power voltage to the OTP memory cell array in response to a read operation of the OTP memory cell array, and an Electro-Static Discharge (ESD) protection circuit configured to turn off the first switching element in response to a flow of ESD voltage from the voltage supply pad.

Power switch circuit and method providing power supply to memory device

A sense amplifier driving device is disclosed. The device includes a cell array, a bias current generation unit connected to the cell array via a bit line, a sense amplifier connected to the cell array via the bit line to detect and amplify a bit line voltage of the bit line, and a latch unit that outputs the detected bit line voltage as an output signal in a read operation of the cell array. The sense amplifier includes a precharge transistor that precharges the bit line based on a first voltage during a programming operation of the cell array, a read voltage convey unit connected to the bit line and operates during a read operation of the cell array, and a sensing unit that outputs an output voltage based on the bit line voltage.

Sense amplifier driving device

Provided is a one-time programmable (OTP) memory device, which includes a data input circuit that receives a supply voltage and applies the supply voltage to one of a plurality of bit lines that is selected by a write switch, and an OTP memory cell array including a plurality of OTP memory cells arranged in a plurality of rows and columns. The OTP memory cells on the same row connected to the same bit line. The OTP memory device also includes a column decoder that selects one of the plurality of columns of the OTP memory cells to apply the supply voltage thereto, and a detection amplifier that performs a read operation of the OTP memory cells connected to one of the plurality of bit lines that is selected by a read switch.

One-time programmable memory device

A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier. The sense amplifier is connected to the bit line, receives a first control signal, and detects and amplifies a bit line signal of the bit line. The sense amplifier includes a precharge device that is turned on or turned off based on a read control signal, and a transistor output unit that outputs an output voltage based on the bit line signal when the precharge device is turned off.

An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.

OTP cell having a reduced layout area

Provided is a power switch circuit that includes a first level shifter that, in response to execution of a programming operation of a one-time programmable (OTP) memory cell array, turns on a first switching device that has received a supply voltage from an external supply voltage pad. The power switch circuit also include a second level shifter that, in response to execution of the programming operation, turns on a second switching device connected to the first switching device, to provide the supply voltage to the OTP memory cell array. The power switch circuit further includes a third level shifter that, in response to execution of a read operation of the OTP memory cell array, turns on a third switching device to provide a power voltage, which is internally generated within the power switch circuit, to the OTP memory cell array.

Power switch circuit

A non-volatile semiconductor storage device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate, wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact.

One time programmable (OTP) cell having improved programming reliability

An OTP memory device includes an OTP memory cell array including OTP memory cells driven by an external supply voltage, the OTP memory cells comprising bit lines arrayed in rows and columns; data input circuits respectively connected to the rows of the OTP memory cells and configured to select a row of the OTP memory cells to which the supply voltage is to be applied; a column decoder connected to each column of the OTP memory cells and configured to select columns of the OTP memory cells to which the supply voltage is to be applied; and a detection amplifier connected to the bit line and configured to perform a read operation of the OTP memory cells.

One-time programmable (OTP) memory device

An anti-fuse device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a salicide layer formed on a first portion of the gate electrode such that a second portion of the gate electrode omits the salicide layer, wherein a hard breakdown of at least a portion of the gate insulating film at a time of programming the anti-fuse device.

One time programmable (OTP) cell and an OTP memory array using the same

A method and circuit for updating a software register is disclosed, wherein the software register is updated using data received through a data I/O pad, and the updated data is read and transferred to the outside through the data I/O pad. The disclosed method of updating the software register includes the steps of receiving necessary data from a data I/O pad, writing the data received from the data I/O pad into the software register, thereby updating the software register, and reading the updated data from the software register, and transferring the data to the outside through the data I/O pad.

Method and circuit for updating a software register in semiconductor memory device

A pseudo SRAM which can perform read and write operations of data in a continuous burst mode in such a manner that it continuously generates burst row and column address signals, which gradually rise, based on external address signals that have already been received until new external address signals are received.

Pseudo SRAM capable of operating in continuous burst mode and method of controlling burst mode operation thereof

The present invention discloses a circuit for generating a wait signal in a semiconductor device. Even if an address input enable signal is synchronized with a clock and continuously or irregularly inputted, the circuit for generating the wait signal in the semiconductor device generates the wait signal suitable for a latency counter by using the finally-inputted address input enable signal. In addition, the circuit for generating the wait signal in the semiconductor device generates the wait signals having various pulse widths to be suitable for various latency counters, and enables the object wait signal earlier than data input or output by one clock, or simultaneously with data input or output.

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Seoul, South Korea

Duk Ju Jeong