Samsung Electronics Co., Ltd.

Duk-ha Park

Hyung-Dong Kim

Hi-Choon Lee

Byung-sick Moon

Sung-min Yim

Jang-Seok Choi

A semiconductor memory device with an improved redundancy scheme is provided. The semiconductor memory device includes at least one memory block having a plurality of memory banks that are arranged in a column direction. Each memory bank includes a plurality of normal memory cells, which are arranged according to a row and column structure, and at least one redundancy memory cell to replace defective memory cells. At least one memory bank, adjacent to an edge of photo shot or an edge of chip, among the plurality of memory banks includes more redundancy lines than the other memory banks. In the semiconductor memory device, when memory banks have different numbers of defective memory cells to be repaired, the number of redundancy memory cells of each memory bank is differently set, thus increasing the yield.

Semiconductor memory device having improved redundancy scheme

A semiconductor memory device having a mesh-type structure of a precharge voltage line is provided. The semiconductor memory device includes a plurality of memory cell arrays, a plurality of bit line precharge circuit units, and a first precharge voltage line and a second precharge voltage line. Each of the plurality of memory cell arrays include a plurality of memory cells and a plurality of bit line pairs for outputting and receiving data to and from each of the memory cells and are arranged in a matrix. The plurality of bit line precharge circuit units precharge and equalize corresponding bit line pairs of the memory cell arrays into predetermined precharge voltages. The first precharge voltage line and the second precharge voltage line are arranged in a mesh in each region between the plurality of memory cell arrays. During a first mode of operation, the first precharge voltage line and the second precharge voltage line supply a common precharge voltage and during a second precharge voltage line, precharge voltages having different levels are supplied at the first and the second precharge voltage lines to precharge memory cells adjacent to one another with different precharge voltages.

Semiconductor memory device having mesh-type structure of precharge voltage line

A semiconductor memory device internal voltage generator and internal voltage generating method are disclosed. The device and method are capable of supplying a uniform amount of electric charge and generating a stable internal voltage, despite variations in an external voltage. The internal voltage generator includes a PMOS driving transistor having a source connected to the external voltage, a gate connected to a driving signal, and a drain that supplies the internal voltage. The interval voltage generator also includes a driving signal generator that generates the driving signal in response to a control signal. The driving signal generator maintains a voltage between the gate and source of the PMOS driving transistor at a substantially uniform voltage level despite variations in the external voltage.

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Suwon, South Korea

Duk-ha Park