Samsung Electronics Co., Ltd.

Dug-dong Kang

Yun-Seung Shin

Young-Jae Choi

Young-woo Seo

Joo-young Yoon

Chang-gyu Hwang

Sun-cheol Hong

Won-cheol Hong

Ki-man Han

Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of simultaneously forming storage electrode and bit line contact regions of first conductivity type in a semiconductor region of second conductivity type. The contact regions preferably receive a double dose of first conductivity type dopants. This double dose compensates for etching damage caused during processing and improves the memory cell's refresh characteristics. The preferred methods of forming DRAM memory cells include the steps of forming an electrically insulating layer on a face of a semiconductor substrate containing a region of second conductivity type therein (e.g., P-type) extending to the face, and then forming a word line (or segment thereof) on the electrically insulating layer, opposite the region of second conductivity type. Contact regions of first conductivity type for a storage electrode and bit line are then formed at the same time at adjacent opposing edges of the word lines by implanting dopants of first conductivity type into the region of second conductivity type using the word line as an implant mask. A storage electrode of a capacitor is then formed on (or coupled to) the storage electrode contact region adjacent a first edge of the word line and a bit line is also preferably formed on (or coupled to) the bit line contact region adjacent a second edge of the word line. The bit line contact region and storage electrode contact region preferably receive a double dose of first conductivity type dopants by performing a first ion implant step, forming sidewall spacers on the first and second edges of the word line and then performing a second ion implant step using the sidewall spacers as an implant mask.

Methods of forming integrated circuit memory devices having improved bit

A method for forming an electrode for an integrated circuit device includes the steps of forming a first conductive layer on a surface of a microelectronic substrate, and forming a patterned photoresist layer on the first conductive layer. A spacer is formed along sidewalls of the patterned photoresist layer, and the first conductive layer is etched to a predetermined depth less than a thickness of the first conductive layer using the patterned photoresist layer and the spacer as an etch mask thereby defining a hole in the first conductive layer. A protective layer is formed in the hole which covers exposed portions of the first conductive layer, and the patterned photoresist layer is removed. The first conductive layer is then etched using the spacer and the protective layer as an etching mask to form a vertical electrode structure. Related structures are also discussed.

Methods for forming vertical electrode structures and related structures

A method for manufacturing first electrode of a capacitor of a semiconductor device is disclosed. After forming a polycrystalline layer composed of grains with microscopic structure to include an impurity in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged. The micro-trenches or micro-pillars are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains are formed by epitaxial growth, so that cell capacitance can be further increased. The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily.

Method for manufacturing a capacitor of a semiconductor device

Growing community of inventors

Kyungki-do, South Korea

Dug-dong Kang