Hon Hai Precision Industry Co., Ltd.

Mediatek Corporation

Duen-Yi Ho

Chun-Jen Chen

Shou-Kuo Hsu

Tsung-Sheng Huang

Wei-Chieh Chou

Cheng-Shien Li

Yung-Chieh Chen

Hsien-Chuan Liang

Shin-Ting Yen

Shen-Chun Li

Chun-Sheng Chen

Yu-Chang Pai

Ying-Tso Lai

Hsing-Chih Liu

Shang-Pin Chen

Che-Hung Kuo

Sheng-Mou Lin

Hung-Chuan Chen

Yi-Jyun Lee

A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

Semiconductor package structure

A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.

Semiconductor devices and methods for enhancing signal integrity of an interface provided by a semiconductor device

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad.

Semiconductor package assembly with redistribution layer (RDL) trace

A method for calculating efficiency of a power supply system includes: displaying a parameter selection interface on the display unit for selecting power supply parameters and transmission line parameters. Obtaining power supply parameters and transmission line parameters selected by the user via the parameter selection interface when determining the user has finished the selection. Determining a efficiency of a selected power supply of the power supply parameters according to the relationship table, and calculating a sum efficiency according to the obtained power supply parameters and the transmission line parameters and the efficiency of the selected power supply. And calculating a total efficiency of the power supply system according to each sum efficiency when determining that all of the power supplies of the power supply system have been selected.

Electronic device and method for calculating efficiency of simulative power supply system

A motherboard includes a printed circuit board (PCB), a central processing unit (CPU), a regulator, a first memory adaptor, and a second memory adaptor. The PCB includes a top surface, a bottom surface, a plurality of first soldering pads and first leads arranged on the top surface, and a plurality of second leads arranged between the top surface and the bottom surface. The PCB defines a plurality of first vias, second vias, and power vias. The CPU is connected to the first vias. The voltage regulator is connected to the power vias. The first memory adaptor neighbors to the regulator and is surface-mount soldered to the first soldering pads. The first soldering pads are connected to the first vias by first leads. The second memory adaptor is soldered to the second vias. The second vias are connected to the first vias by the second leads.

Motherboard capable of reducing electromagnetic interference

A power supply device includes a power supply unit and a feedback control unit. The power supply unit is configured for generating an electric potential to be provided to a load. The feedback control unit detects the electric potential and adjusts relevant parameters of the electrical potential to achieve predetermined values. The feedback control unit includes a first feedback circuit and a second feedback circuit electrically connected in series.

Power supply device

A current balance circuit includes a first and a second current sensors, an averager, a first and a second control modules, and a first and a second rheostat elements. The first and second current sensors receive a first current and a second current from a power source respectively and convert the first and second currents into a first and a second voltages. The averager receives the first and second voltages and calculates to obtain an average voltage. The first and second control modules receive the first voltage, the second voltage, and the average voltage, to obtain a first and a second control signals, to control current conduction ability of the first and second rheostat elements, to make the first and second currents keep a dynamic balance.

Current balance circuit to keep dynamic balance between currents in power passages of power connector

An electronic device reads a layout file of a printed circuit board (PCB) to be manufactured from a storage device, obtains length information and section area information of copper cladding distributed on power source areas and ground trace areas in each of one or more layers of the PCB to be manufactured by analyzing the layout file, and calculates power loss in each of the one or more layers according to the length information, the section area information, a resistance value of the copper cladding, and preset parameters of a power supply module and an integrated circuit (IC) load to be located on the PCB. In response to a determination that the power loss in the layer exceeds a preset range, the electronic device indicates the locations of the power source areas and the ground trace areas of a layer in the PCB layout file which need to be redesigned.

Electronic device and simulation method for checking printed circuit board power loss

A printed circuit board includes a first to a fifth connector pads, a first to an eighth coupling capacitor pads, a first to a tenth transmission lines, a first via and a second via, a first to a fourth sharing pads, and a voltage converting circuit. The printed circuit board is operable to selectively support different types of connectors.

Printed circuit board

A printed circuit board includes a top layer and a bottom layer. A power supply and an electronic component are located on the top layer. The power supply is connected to the top layer and the bottom layer through a first via. A number of second vias extends through the top layer and the bottom layer, and is electrically connected to the top layer and the bottom layer. A right-angled triangular void area without vias defined therein is formed on the printed circuit board, between the second vias and the electronic component. The second vias are arranged on a hypotenuse of the void area.

A voltage regulating circuit includes a pulse width modulation controller, a current sense circuit, a voltage feedback circuit, and a gain-and-bias circuit. The current sense circuit includes an inductor and a capacitor. The voltage feedback circuit includes first and second resistors. The gain-and-bias circuit includes an operational amplifier. A first terminal of the capacitor is connected to an inverting input terminal of the operational amplifier through a third resistor. A second terminal of the capacitor is connected to a non-inverting input terminal of the operational amplifier through a fourth resistor. The inverting input terminal of the amplifier is connected to an output terminal of the operational amplifier through a fifth resistor. The non-inverting input terminal of the operational amplifier is grounded through a sixth resistor. The output terminal of the operational amplifier is connected to the node between the first and second resistors through a seventh resistor.

Voltage regulation circuit

A printed circuit board (PCB) includes first to fourth layers. A power supply is arranged on the first layer. An electronic component is arranged on the fourth layer. A first via and a second via extend through the PCB and are electrically connected to the electronic component. The PCB further includes third to seventh vias. A length of a transmission path of the current flows from the power supply to electronic component through the third via and the seventh via is almost the same as a length of a transmission path of the current flows from the power supply to the electronic component through the fourth to sixth vias.

A printed circuit board (PCB) can prevent electrostatic discharge. A number of vias are embedded in the PCB. A circular insulated member is disposed between each via and the number of vias. Each via includes a layer of metal coated on an inner wall of a corresponding insulated member and a through hole bounded by the corresponding insulated member. An acute angle between two tangents which pass through a point of intersection of two overlapped insulated members is greater than twenty degrees.

Printed circuit board to prevent electrostatic discharge and manufacturing method thereof

A system for optimizing a current overload protection circuit includes an input device, a data storage device, a central processing device, and a display. The central processing device includes a storage module, a control module, and a calculation module. The storage module stores a VI application therein. The control module receives instructions from the input device and selects virtual electronic components of the current overload protection circuit from the data storage device and connection of the selected electronic components. The current overload protection circuit is completed and run in the VI application; electronic components significantly affecting the maximum protection current are labeled. The calculation module calculates normal distribution samples of the current overload protection circuit based on the labeled electronic components. The display shows whether the current overload protection circuit meets a process capability standard.

System and method for optimizing current overload protection circuit

A system and method that can analyze a temperature rise of a printed circuit board (PCB). The system and method receives attribute parameters of the PCB from an input device, and generates a temperature rise formula according to the received attribute parameters. Additionally, the system and method calculates a temperature rise of a local area surrounding each component on the PCB according to the temperature rise formula.

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Taipei Hsien, Taiwan

Duen-Yi Ho